Lines Matching refs:ST

69                          const RISCVSubtarget &ST, MachineRegisterInfo &MRI);
71 const RISCVSubtarget &ST, MachineRegisterInfo &MRI);
73 const RISCVSubtarget &ST, MachineRegisterInfo &MRI);
120 const RISCVSubtarget &ST, in hasAllNBitUsers() argument
200 if (Bits >= (ST.getXLen() / 2)) in hasAllNBitUsers()
219 if (Bits >= (ST.getXLen() - UserMI->getOperand(2).getImm())) in hasAllNBitUsers()
244 if (Bits >= Log2_32(ST.getXLen())) in hasAllNBitUsers()
256 if (OpIdx == 2 && Bits >= Log2_32(ST.getXLen())) in hasAllNBitUsers()
344 static bool hasAllWUsers(const MachineInstr &OrigMI, const RISCVSubtarget &ST, in hasAllWUsers() argument
346 return hasAllNBitUsers(OrigMI, ST, MRI, 32); in hasAllWUsers()
396 static bool isSignExtendedW(Register SrcReg, const RISCVSubtarget &ST, in isSignExtendedW() argument
597 if (hasAllWUsers(*MI, ST, MRI)) { in isSignExtendedW()
632 const RISCVSubtarget &ST, in removeSExtWInstrs() argument
651 if (!hasAllWUsers(MI, ST, MRI) && in removeSExtWInstrs()
652 !isSignExtendedW(SrcReg, ST, MRI, FixableDefs)) in removeSExtWInstrs()
684 const RISCVSubtarget &ST, in stripWSuffixes() argument
699 if (hasAllWUsers(MI, ST, MRI)) { in stripWSuffixes()
711 const RISCVSubtarget &ST, in appendWSuffixes() argument
745 if (hasAllWUsers(MI, ST, MRI)) { in appendWSuffixes()
766 const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>(); in runOnMachineFunction() local
767 const RISCVInstrInfo &TII = *ST.getInstrInfo(); in runOnMachineFunction()
769 if (!ST.is64Bit()) in runOnMachineFunction()
773 MadeChange |= removeSExtWInstrs(MF, TII, ST, MRI); in runOnMachineFunction()
775 if (!(DisableStripWSuffix || ST.preferWInst())) in runOnMachineFunction()
776 MadeChange |= stripWSuffixes(MF, TII, ST, MRI); in runOnMachineFunction()
778 if (ST.preferWInst()) in runOnMachineFunction()
779 MadeChange |= appendWSuffixes(MF, TII, ST, MRI); in runOnMachineFunction()