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Searched refs:SRLI (Results 1 – 23 of 23) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp1215 SDNode *SRLI = CurDAG->getMachineNode( in Select() local
1216 RISCV::SRLI, DL, VT, SDValue(SLLI, 0), in Select()
1218 ReplaceNode(Node, SRLI); in Select()
1267 SDNode *SRLI = CurDAG->getMachineNode( in Select() local
1268 Subtarget->is64Bit() ? RISCV::SRLIW : RISCV::SRLI, DL, VT, in Select()
1270 ReplaceNode(Node, SRLI); in Select()
1296 SDNode *SRLI = CurDAG->getMachineNode( in Select() local
1297 RISCV::SRLI, DL, VT, SDValue(SLLI, 0), in Select()
1299 ReplaceNode(Node, SRLI); in Select()
1445 SDNode *SRLI = CurDAG->getMachineNode( in Select() local
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H A DRISCVGISel.td151 def : Pat<(zext (i32 GPR:$src)), (SRLI (i64 (SLLI GPR:$src, 32)), 32)>;
155 (SRLI (XLenVT (SLLI GPR:$src, 16)), 16)>;
159 (SRLI (XLenVT (SLLI GPR:$src, 48)), 48)>;
161 (SRLI (XLenVT (SLLI GPR:$src, 48)), 48)>;
H A DRISCVInstrInfoZb.td735 // Use SRLI to clear the LSBs and SHXADD_UW to mask and shift.
738 (sh1add_uw (XLenVT (SRLI GPR:$rs1, 1)), GPR:$rs2)>;
745 // Use SRLI to clear the LSBs and SHXADD_UW to mask and shift.
748 (sh2add_uw (XLenVT (SRLI GPR:$rs1, 2)), GPR:$rs2)>;
755 // Use SRLI to clear the LSBs and SHXADD_UW to mask and shift.
758 (sh3add_uw (XLenVT (SRLI GPR:$rs1, 3)), GPR:$rs2)>;
779 // Match a shifted 0xffffffff mask. Use SRLI to clear the LSBs and SLLI_UW to
782 (SLLI_UW (XLenVT (SRLI GPR:$rs1, Shifted32OnesMask:$mask)),
H A DRISCVOptWInstrs.cpp210 case RISCV::SRLI: { in hasAllNBitUsers()
384 case RISCV::SRLI: in isSignExtendingOpW()
H A DRISCVAsmPrinter.cpp768 MCInstBuilder(RISCV::SRLI) in EmitHwasanMemaccessSymbols()
787 MCInstBuilder(RISCV::SRLI).addReg(RISCV::X7).addReg(Reg).addImm(56), in EmitHwasanMemaccessSymbols()
H A DRISCVInstrInfo.td787 def SRLI : Shift_ri<0b00000, 0b101, "srli">,
1177 (SRLI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt)>;
1448 def : PatGprUimmLog2XLen<srl, SRLI>;
1475 (SLLI (i64 (SRLI $rs, (TrailingZeros imm:$mask))),
1478 (SRLI (XLenVT (SLLI $rs, (XLenSubTrailingOnes imm:$mask))),
2074 def : Pat<(i64 (and GPR:$rs1, 0xffffffff)), (SRLI (i64 (SLLI GPR:$rs1, 32)), 32)>;
2079 (SRLI (i64 (SLLI GPR:$rs1, 32)), (ImmSubFrom32 uimm5:$shamt))>;
H A DRISCVExpandPseudoInsts.cpp228 case RISCV::PseudoCCSRLI: NewOpc = RISCV::SRLI; break; in expandCCOp()
H A DRISCVVectorPeephole.cpp250 } else if (Def->getOpcode() == RISCV::SRLI) { in convertToVLMAX()
H A DRISCVRegisterInfo.cpp960 case RISCV::SRLI: in getRegAllocationHints()
H A DRISCVInstrInfoC.td928 def : CompressPat<(SRLI GPRC:$rs1, GPRC:$rs1, uimmlog2xlennonzero:$imm),
H A DRISCVFrameLowering.cpp1128 BuildMI(MBB, MBBI, DL, TII->get(RISCV::SRLI), VR) in emitPrologue()
H A DRISCVInstrInfo.cpp1659 case RISCV::SRLI: return RISCV::PseudoCCSRLI; break; in getPredicatedOpcode()
4227 case RISCV::SRLI: in simplifyInstruction()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMatInt.cpp30 case RISCV::SRLI: in getInstSeqCost()
223 TmpSeq.emplace_back(RISCV::SRLI, LeadingZeros); in generateInstSeqLeadingZeros()
235 TmpSeq.emplace_back(RISCV::SRLI, LeadingZeros); in generateInstSeqLeadingZeros()
576 case RISCV::SRLI: in getOpndKind()
/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/RISCV/
H A DRISCVInstructions.h143 R_SHAMT_TYPE_INST(SRLI);
278 LWU, LD, SD, SLLI, SRLI, SRAI, ADDIW, SLLIW, SRLIW, SRAIW, ADDW, SUBW, SLLW,
H A DRISCVCInstructions.h241 return SRLI{rd, rd, uint8_t(shamt)}; in DecodeC_SRLI()
H A DEmulateInstructionRISCV.cpp444 {"SRLI", 0xF800707F, 0x5013, DecodeRShamtType<SRLI>},
885 bool operator()(SRLI inst) { in operator ()()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVInstructionSelector.cpp256 case RISCV::SRLI: { in hasAllNBitUsers()
431 .buildInstr(RISCV::SRLI, {DstReg}, {RegY}) in selectSHXADDOp()
443 .buildInstr(RISCV::SRLI, {DstReg}, {RegY}) in selectSHXADDOp()
/freebsd/contrib/llvm-project/lld/ELF/Arch/
H A DRISCV.cpp70 SRLI = 0x5013, enumerator
240 write32le(buf + 20, itype(SRLI, X_T1, X_T1, ctx.arg.is64 ? 1 : 2)); in writePltHeader()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsScheduleP5600.td438 def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(SRL|SRLI)_[BHWD]$")>;
H A DMipsScheduleGeneric.td1559 def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(SRL|SRLI)_[BHWD]$")>;
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaInstrInfo.td160 def SRLI : RRR_Inst<0x00, 0x01, 0x04, (outs AR:$r), (ins AR:$t, uimm4:$sa),
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp3594 unsigned SecondOpcode = SignExtend ? RISCV::SRAI : RISCV::SRLI; in emitPseudoExtend()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp6771 if (ConstantSDNode *SRLI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) { in visitANDLike() local
6777 APInt SRLC = SRLI->getAPIntValue(); in visitANDLike()