| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMTargetTransformInfo.cpp | 1388 { ISD::SREM, MVT::v1i64, 1 * FunctionCallDivCost}, in getArithmeticInstrCost()
1392 { ISD::SREM, MVT::v2i32, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
1396 { ISD::SREM, MVT::v4i16, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
1400 { ISD::SREM, MVT::v8i8, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
1405 { ISD::SREM, MVT::v2i64, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
1409 { ISD::SREM, MVT::v4i32, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
1413 { ISD::SREM, MVT::v8i16, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
1417 { ISD::SREM, MVT::v16i8, 16 * FunctionCallDivCost}, in getArithmeticInstrCost()
2228 case ISD::SREM: in maybeLoweredToCall()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86TargetTransformInfo.cpp | 341 if ((ISD == ISD::SDIV || ISD == ISD::SREM) && in getArithmeticInstrCost()
351 if (ISD == ISD::SREM) { in getArithmeticInstrCost()
441 { ISD::SREM, MVT::v16i32, { 8 } }, // pmuludq+mul+sub sequence in getArithmeticInstrCost()
482 { ISD::SREM, MVT::v8i32, { 8 } }, // pmuludq+mul+sub sequence in getArithmeticInstrCost()
523 { ISD::SREM, MVT::v8i32, { 18 } }, // 2*pmuludq+mul+sub sequence + split. in getArithmeticInstrCost()
554 { ISD::SREM, MVT::v4i32, { 8 } }, // pmuludq+mul+sub sequence in getArithmeticInstrCost()
569 { ISD::SREM, MVT::v64i8, { 16 } }, // 2*ext+2*pmulhw+mul+sub sequence in getArithmeticInstrCost()
574 { ISD::SREM, MVT::v32i16, { 8 } }, // vpmulhw+mul+sub sequence in getArithmeticInstrCost()
587 { ISD::SREM, MVT::v64i8, { 32 } }, // 4*ext+4*pmulhw+mul+sub sequence in getArithmeticInstrCost()
592 { ISD::SREM, MVT::v32i16, { 16 } }, // 2*vpmulhw+mul+sub sequence in getArithmeticInstrCost()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 264 SREM, enumerator
|
| H A D | BasicTTIImpl.h | 1063 if (ISD == ISD::UREM || ISD == ISD::SREM) {
1064 bool IsSigned = ISD == ISD::SREM;
|
| H A D | SDPatternMatch.h | 864 return BinaryOpc_match<LHS, RHS>(ISD::SREM, L, R);
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 1935 case ISD::SREM: in selectDivRem()
1959 unsigned MFOpc = (ISDOpcode == ISD::SREM || ISDOpcode == ISD::UREM) in selectDivRem()
2060 if (!selectBinaryOp(I, ISD::SREM)) in fastSelectInstruction()
2061 return selectDivRem(I, ISD::SREM); in fastSelectInstruction()
|
| H A D | MipsSEISelLowering.cpp | 278 setOperationAction(ISD::SREM, MVT::i32, Legal); in MipsSETargetLowering()
325 setOperationAction(ISD::SREM, MVT::i64, Legal); in MipsSETargetLowering()
376 setOperationAction(ISD::SREM, Ty, Legal); in addMSAIntType()
2096 return DAG.getNode(ISD::SREM, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFISelLowering.cpp | 112 setOperationAction(ISD::SREM, VT, Custom); in BPFTargetLowering()
326 case ISD::SREM: in LowerOperation()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGBuilder.h | 554 void visitSRem(const User &I) { visitBinary(I, ISD::SREM); } in visitSRem()
|
| H A D | LegalizeVectorOps.cpp | 361 case ISD::SREM: in LegalizeOp()
1249 case ISD::SREM: in Expand()
2158 assert((Node->getOpcode() == ISD::SREM || Node->getOpcode() == ISD::UREM) && in ExpandREM()
|
| H A D | SelectionDAGDumper.cpp | 286 case ISD::SREM: return "srem"; in getOperationName()
|
| H A D | LegalizeDAG.cpp | 3911 case ISD::SREM: in ExpandNode()
5157 case ISD::SREM: in ConvertNodeToLibcall()
5440 case ISD::SREM: in PromoteNode()
5462 case ISD::SREM: in PromoteNode()
|
| H A D | SelectionDAG.cpp | 4204 case ISD::SREM: { in computeKnownBits()
5110 case ISD::SREM: in ComputeNumSignBits()
6702 case ISD::SREM: in FoldValue()
6765 case ISD::SREM: in isUndef()
7521 case ISD::SREM: in getNode()
7866 case ISD::SREM: in getNode()
7891 case ISD::SREM: in getNode()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 136 setOperationAction(ISD::SREM, MVT::i8, Promote); in MSP430TargetLowering()
142 setOperationAction(ISD::SREM, MVT::i16, LibCall); in MSP430TargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 648 ISD::SREM, ISD::SRL, ISD::SSHLSAT, ISD::SSUBO, in NVPTXTargetLowering()
808 setI16x2OperationAction(ISD::SREM, MVT::v2i16, Legal, Custom); in NVPTXTargetLowering()
842 ISD::MUL, ISD::SHL, ISD::SREM, ISD::UREM, ISD::VSELECT, in NVPTXTargetLowering()
2952 case ISD::SREM: in LowerOperation()
5321 assert(N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM); in PerformREMCombine()
5330 bool IsSigned = N->getOpcode() == ISD::SREM; in PerformREMCombine()
5806 case ISD::SREM: in PerformDAGCombine()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/ |
| H A D | XtensaISelLowering.cpp | 154 setOperationAction(ISD::SREM, MVT::i32, Legal); in XtensaTargetLowering()
159 setOperationAction(ISD::SREM, MVT::i32, Expand); in XtensaTargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 987 case ISD::SREM: in canOpTrap()
1871 case SRem: return ISD::SREM; in InstructionOpcodeToISD()
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | VPIntrinsics.def | 167 HELPER_REGISTER_BINARY_INT_VP(vp_srem, VP_SREM, SRem, SREM)
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 156 setOperationAction(ISD::SREM, MVT::i8, Expand); in AVRTargetLowering()
157 setOperationAction(ISD::SREM, MVT::i16, Expand); in AVRTargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 159 setOperationAction({ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM}, MVT::i32, in LoongArchTargetLowering()
300 setOperationAction({ISD::MUL, ISD::SDIV, ISD::SREM, ISD::UDIV, ISD::UREM}, in LoongArchTargetLowering()
367 setOperationAction({ISD::MUL, ISD::SDIV, ISD::SREM, ISD::UDIV, ISD::UREM}, in LoongArchTargetLowering()
3791 case ISD::SREM: in getLoongArchWOpcode()
4028 case ISD::SREM: in ReplaceNodeResults()
5438 return DAG.getNode(ISD::SREM, DL, N->getValueType(0), N->getOperand(1), in performINTRINSIC_WO_CHAINCombine()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 4630 case ISD::SREM: in selectRem()
5129 if (!selectBinaryOp(I, ISD::SREM)) in fastSelectInstruction()
5130 return selectRem(I, ISD::SREM); in fastSelectInstruction()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelLowering.cpp | 58 setOperationAction(ISD::SREM, MVT::i32, Expand); in CSKYTargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.cpp | 108 setOperationAction(ISD::SREM, MVT::i32, Expand); in LanaiTargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1665 setOperationAction(ISD::SREM, MVT::i32, Expand); in SparcTargetLowering()
1672 setOperationAction(ISD::SREM, MVT::i64, Expand); in SparcTargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1668 {ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM, in HexagonTargetLowering()
1716 ISD::SREM, ISD::UREM, ISD::SDIVREM, ISD::UDIVREM, ISD::SADDO, in HexagonTargetLowering()
|