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Searched refs:SREM (Results 1 – 25 of 46) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp1363 { ISD::SREM, MVT::v1i64, 1 * FunctionCallDivCost}, in getArithmeticInstrCost()
1367 { ISD::SREM, MVT::v2i32, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
1371 { ISD::SREM, MVT::v4i16, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
1375 { ISD::SREM, MVT::v8i8, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
1380 { ISD::SREM, MVT::v2i64, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
1384 { ISD::SREM, MVT::v4i32, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
1388 { ISD::SREM, MVT::v8i16, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
1392 { ISD::SREM, MVT::v16i8, 16 * FunctionCallDivCost}, in getArithmeticInstrCost()
2104 case ISD::SREM: in maybeLoweredToCall()
H A DARMISelLowering.cpp213 setOperationAction(ISD::SREM, VT, Expand); in addTypeForNEON()
297 setOperationAction(ISD::SREM, VT, Expand); in addMVEVectorTypes()
1240 setOperationAction(ISD::SREM, MVT::i32, Expand); in ARMTargetLowering()
1247 setOperationAction(ISD::SREM, MVT::i64, Custom); in ARMTargetLowering()
10605 case ISD::SREM: return LowerREM(Op.getNode(), DAG); in LowerOperation()
10743 case ISD::SREM: in ReplaceNodeResults()
20680 N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM) && in getDivRemLibcall()
20683 N->getOpcode() == ISD::SREM; in getDivRemLibcall()
20698 N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM) && in getDivRemArgList()
20701 N->getOpcode() == ISD::SREM; in getDivRemArgList()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h251 SREM, enumerator
H A DSDPatternMatch.h607 return BinaryOpc_match<LHS, RHS, false>(ISD::SREM, L, R);
H A DBasicTTIImpl.h936 if (ISD == ISD::UREM || ISD == ISD::SREM) {
937 bool IsSigned = ISD == ISD::SREM;
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp342 if ((ISD == ISD::SDIV || ISD == ISD::SREM) && in getArithmeticInstrCost()
352 if (ISD == ISD::SREM) { in getArithmeticInstrCost()
442 { ISD::SREM, MVT::v16i32, { 8 } }, // pmuludq+mul+sub sequence in getArithmeticInstrCost()
483 { ISD::SREM, MVT::v8i32, { 8 } }, // pmuludq+mul+sub sequence in getArithmeticInstrCost()
524 { ISD::SREM, MVT::v8i32, { 18 } }, // 2*pmuludq+mul+sub sequence + split. in getArithmeticInstrCost()
555 { ISD::SREM, MVT::v4i32, { 8 } }, // pmuludq+mul+sub sequence in getArithmeticInstrCost()
570 { ISD::SREM, MVT::v64i8, { 16 } }, // 2*ext+2*pmulhw+mul+sub sequence in getArithmeticInstrCost()
575 { ISD::SREM, MVT::v32i16, { 8 } }, // vpmulhw+mul+sub sequence in getArithmeticInstrCost()
588 { ISD::SREM, MVT::v64i8, { 32 } }, // 4*ext+4*pmulhw+mul+sub sequence in getArithmeticInstrCost()
593 { ISD::SREM, MVT::v32i16, { 16 } }, // 2*vpmulhw+mul+sub sequence in getArithmeticInstrCost()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp1923 case ISD::SREM: in selectDivRem()
1944 unsigned MFOpc = (ISDOpcode == ISD::SREM || ISDOpcode == ISD::UREM) in selectDivRem()
2045 if (!selectBinaryOp(I, ISD::SREM)) in fastSelectInstruction()
2046 return selectDivRem(I, ISD::SREM); in fastSelectInstruction()
H A DMipsSEISelLowering.cpp239 setOperationAction(ISD::SREM, MVT::i32, Legal); in MipsSETargetLowering()
286 setOperationAction(ISD::SREM, MVT::i64, Legal); in MipsSETargetLowering()
337 setOperationAction(ISD::SREM, Ty, Legal); in addMSAIntType()
2052 return DAG.getNode(ISD::SREM, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp104 setOperationAction(ISD::SREM, VT, Custom); in BPFTargetLowering()
315 case ISD::SREM: in LowerOperation()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp350 case ISD::SREM: in LegalizeOp()
1113 case ISD::SREM: in Expand()
1830 assert((Node->getOpcode() == ISD::SREM || Node->getOpcode() == ISD::UREM) && in ExpandREM()
H A DSelectionDAGBuilder.h555 void visitSRem(const User &I) { visitBinary(I, ISD::SREM); } in visitSRem()
H A DSelectionDAGDumper.cpp269 case ISD::SREM: return "srem"; in getOperationName()
H A DLegalizeDAG.cpp3772 case ISD::SREM: in ExpandNode()
4948 case ISD::SREM: in ConvertNodeToLibcall()
5229 case ISD::SREM: in PromoteNode()
5251 case ISD::SREM: in PromoteNode()
H A DSelectionDAG.cpp3967 case ISD::SREM: { in computeKnownBits()
4835 case ISD::SREM: in ComputeNumSignBits()
6288 case ISD::SREM: in FoldValue()
6351 case ISD::SREM: in isUndef()
6976 case ISD::SREM: in getNode()
7343 case ISD::SREM: in getNode()
7365 case ISD::SREM: in getNode()
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp137 setOperationAction(ISD::SREM, MVT::i8, Promote); in MSP430TargetLowering()
143 setOperationAction(ISD::SREM, MVT::i16, LibCall); in MSP430TargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp537 ISD::SREM, ISD::SRL, ISD::SSHLSAT, ISD::SSUBO, in NVPTXTargetLowering()
698 setI16x2OperationAction(ISD::SREM, MVT::v2i16, Legal, Custom); in NVPTXTargetLowering()
732 ISD::LOAD, ISD::MUL, ISD::SHL, ISD::SREM, ISD::UREM, in NVPTXTargetLowering()
2811 case ISD::SREM: in LowerOperation()
5586 assert(N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM); in PerformREMCombine()
5595 bool IsSigned = N->getOpcode() == ISD::SREM; in PerformREMCombine()
6028 case ISD::SREM: in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp888 case ISD::SREM: in canOpTrap()
1784 case SRem: return ISD::SREM; in InstructionOpcodeToISD()
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DVPIntrinsics.def195 HELPER_REGISTER_BINARY_INT_VP(vp_srem, VP_SREM, SRem, SREM)
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp157 setOperationAction(ISD::SREM, MVT::i8, Expand); in AVRTargetLowering()
158 setOperationAction(ISD::SREM, MVT::i16, Expand); in AVRTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp4627 case ISD::SREM: in selectRem()
5123 if (!selectBinaryOp(I, ISD::SREM)) in fastSelectInstruction()
5124 return selectRem(I, ISD::SREM); in fastSelectInstruction()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelLowering.cpp58 setOperationAction(ISD::SREM, MVT::i32, Expand); in CSKYTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp110 setOperationAction(ISD::SREM, MVT::i32, Expand); in LanaiTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVTargetTransformInfo.cpp1736 case ISD::SREM: in getArithmeticInstrCost()
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1674 setOperationAction(ISD::SREM, MVT::i32, Expand); in SparcTargetLowering()
1681 setOperationAction(ISD::SREM, MVT::i64, Expand); in SparcTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1600 {ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM, in HexagonTargetLowering()
1647 ISD::SREM, ISD::UREM, ISD::SDIVREM, ISD::UDIVREM, ISD::SADDO, in HexagonTargetLowering()

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