| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiAluCode.h | 36 SRA = 0x37,
95 case SRA: in lanaiAluCodeToString()
113 .Case("sha", SRA) in stringToLanaiAluCode()
37 SRA = 0x37, global() enumerator
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| H A D | LanaiISelDAGToDAG.cpp | 239 case ISD::SRA: in isdToLanaiAluCode()
240 return AluCode::SRA; in isdToLanaiAluCode()
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| H A D | LanaiMemAluCombiner.cpp | 223 return LPAC::SRA; in mergedAluCode()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86TargetTransformInfo.cpp | 377 { ISD::SRA, MVT::v16i8, { 1, 6, 1, 2 } }, // gf2p8affineqb in getArithmeticInstrCost()
380 { ISD::SRA, MVT::v32i8, { 1, 6, 1, 2 } }, // gf2p8affineqb in getArithmeticInstrCost()
383 { ISD::SRA, MVT::v64i8, { 1, 6, 1, 2 } }, // gf2p8affineqb in getArithmeticInstrCost()
395 { ISD::SRA, MVT::v16i8, { 1, 8, 4, 5 } }, // psrlw, pand, pxor, psubb. in getArithmeticInstrCost()
398 { ISD::SRA, MVT::v32i8, { 1, 9, 4, 5 } }, // psrlw, pand, pxor, psubb. in getArithmeticInstrCost()
401 { ISD::SRA, MVT::v64i8, { 1, 9, 4, 6 } }, // psrlw, pand, pxor, psubb. in getArithmeticInstrCost()
405 { ISD::SRA, MVT::v16i16, { 1, 1, 1, 1 } }, // psrlw in getArithmeticInstrCost()
408 { ISD::SRA, MVT::v32i16, { 1, 1, 1, 1 } }, // psrlw in getArithmeticInstrCost()
420 { ISD::SRA, MVT::v64i8, { 3, 10, 12, 12 } }, // psrlw, pand, pxor, psubb. in getArithmeticInstrCost()
424 { ISD::SRA, MVT::v16i16, { 2, 7, 4, 4 } }, // psraw + split. in getArithmeticInstrCost()
[all …]
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| /freebsd/contrib/telnet/libtelnet/ |
| H A D | auth-proto.h | 98 #ifdef SRA
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| H A D | auth.c | 165 #ifdef SRA
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| H A D | sra.c | 31 #ifdef SRA
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| /freebsd/crypto/heimdal/appl/telnet/libtelnet/ |
| H A D | auth-proto.h | 91 #ifdef SRA
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| H A D | auth.c | 119 #ifdef SRA
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMSelectionDAGInfo.h | 28 case ISD::SRA: return ARM_AM::asr; in getShiftOpcForNode()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZSelectionDAGInfo.cpp | 167 SDValue SRA = DAG.getNode(ISD::SRA, DL, MVT::i32, SHL, in addIPMSequence() local
169 return SRA; in addIPMSequence()
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| H A D | SystemZShortenInst.cpp | 370 TwoOperandOpcode == SystemZ::SRA) { in processBlock()
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| H A D | SystemZISelDAGToDAG.cpp | 935 case ISD::SRA: { in expandRxSBG()
945 if (RxSBG.Opcode == SystemZ::RNSBG || Opcode == ISD::SRA) { in expandRxSBG()
2032 unsigned ShiftOp = TrueOp->getSExtValue() == 1 ? ISD::SRL : ISD::SRA; in expandSelectBoolean()
2051 Result = CurDAG->getNode(ISD::SRA, DL, VT, Result, in expandSelectBoolean()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 85 setOperationAction(ISD::SRA, MVT::i8, Custom); in AVRTargetLowering()
88 setOperationAction(ISD::SRA, MVT::i16, Custom); in AVRTargetLowering()
91 setOperationAction(ISD::SRA, MVT::i32, Custom); in AVRTargetLowering()
313 case ISD::SRA: in LowerShifts()
347 case ISD::SRA: in LowerShifts()
357 case ISD::SRA: in LowerShifts()
403 } else if (Op.getOpcode() == ISD::SRA && ShiftAmount == 6) { in LowerShifts()
408 } else if (Op.getOpcode() == ISD::SRA && ShiftAmount == 7) { in LowerShifts()
442 if (Op.getOpcode() == ISD::SRA) in LowerShifts()
494 case ISD::SRA: in LowerShifts()
[all …]
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| /freebsd/crypto/openssl/test/ |
| H A D | testmldsa65.pem | 39 KE5+mIY+NnSHhMy2gnHe/fClylH9ChgLsR5cHOWhx9WuQgqEjuZv9MMjUsPx/SRA
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| /freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/RISCV/ |
| H A D | RISCVInstructions.h | 134 R_TYPE_INST(SRA);
277 SLTIU, XORI, ORI, ANDI, ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND,
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeIntegerTypes.cpp | 112 case ISD::SRA: in PromoteIntegerResult()
1087 ShiftOp = ISD::SRA; in PromoteIntRes_ADDSUBSHLSAT()
1153 unsigned ShiftOp = Signed ? ISD::SRA : ISD::SRL; in PromoteIntRes_MULFIX()
1255 Res = DAG.getNode(Signed ? ISD::SRA : ISD::SRL, dl, PromotedType, Res, in PromoteIntRes_DIVFIX()
1974 case ISD::SRA: in PromoteIntegerOperand()
2891 case ISD::SRA: in ExpandIntegerResult()
3045 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); in ExpandShiftByConstant()
3047 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH, in ExpandShiftByConstant()
3050 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH, in ExpandShiftByConstant()
3052 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, in ExpandShiftByConstant()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VVPNodes.def | 102 ADD_BINARY_VVP_OP(VVP_SRA,VP_SRA,SRA) REGISTER_PACKED(VVP_SRA)
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| /freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 75 setOperationAction(ISD::SRA, MVT::i8, Custom); in MSP430TargetLowering()
78 setOperationAction(ISD::SRA, MVT::i16, Custom); in MSP430TargetLowering()
344 case ISD::SRA: return LowerShifts(Op, DAG); in LowerOperation()
984 case ISD::SRA: in LowerShifts()
988 Victim = (Opc == ISD::SRA) in LowerShifts()
1201 SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One); in LowerSETCC()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/ |
| H A D | LanaiMCCodeEmitter.cpp | 245 case LPAC::SRA: in getRrMemoryOpValue()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 734 SRA, enumerator
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsExpandPseudo.cpp | 186 BuildMI(sinkMBB, DL, TII->get(Mips::SRA), Dest) in expandAtomicCmpSwapSubword()
491 const unsigned SROp = IsUnsigned ? Mips::SRL : Mips::SRA; in expandAtomicBinOpSubword()
596 BuildMI(sinkMBB, DL, TII->get(Mips::SRA), Dest) in expandAtomicBinOpSubword()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 127 setOperationAction(ISD::SRA, MVT::i32, Custom); in LoongArchTargetLowering()
264 setOperationAction({ISD::SHL, ISD::SRA, ISD::SRL}, VT, Legal); in LoongArchTargetLowering()
311 setOperationAction({ISD::SHL, ISD::SRA, ISD::SRL}, VT, Legal); in LoongArchTargetLowering()
2588 unsigned ShiftRightOp = IsSRA ? ISD::SRA : ISD::SRL; in lowerShiftRightParts()
2605 IsSRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, GRLenMinus1) : Zero; in lowerShiftRightParts()
2628 case ISD::SRA: in getLoongArchWOpcode()
2827 case ISD::SRA: in ReplaceNodeResults()
3125 if (FirstOperandOpc == ISD::SRA || FirstOperandOpc == ISD::SRL) { in performANDCombine()
3180 if (FirstOperandOpc == ISD::SRA || FirstOperandOpc == ISD::SRL || lsb == 0) in performANDCombine()
4045 return DAG.getNode(ISD::SRA, DL, N->getValueType(0), N->getOperand(1), in performINTRINSIC_WO_CHAINCombine()
[all …]
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/ |
| H A D | CodeGenSchedule.cpp | 1919 for (Record *SRA : SRADefs) { in collectProcResources()
1920 if (SRA->getValueInit("SchedModel")->isComplete()) { in collectProcResources()
1921 Record *ModelDef = SRA->getValueAsDef("SchedModel"); in collectProcResources()
1922 addReadAdvance(SRA, getProcModel(ModelDef).Index); in collectProcResources()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCISelLowering.cpp | 131 setOperationAction(ISD::SRA, MVT::i32, Legal); in ARCTargetLowering()
232 SDValue SR = DAG.getNode(ISD::SRA, dl, MVT::i32, LS, in LowerSIGN_EXTEND_INREG()
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