| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiAluCode.h | 36 SRA = 0x37,
95 case SRA: in lanaiAluCodeToString()
113 .Case("sha", SRA) in stringToLanaiAluCode()
37 SRA = 0x37, global() enumerator
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| H A D | LanaiISelDAGToDAG.cpp | 230 case ISD::SRA: in isdToLanaiAluCode()
231 return AluCode::SRA; in isdToLanaiAluCode()
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| H A D | LanaiMemAluCombiner.cpp | 217 return LPAC::SRA; in mergedAluCode()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86TargetTransformInfo.cpp | 376 { ISD::SRA, MVT::v16i8, { 1, 6, 1, 2 } }, // gf2p8affineqb in getArithmeticInstrCost()
379 { ISD::SRA, MVT::v32i8, { 1, 6, 1, 2 } }, // gf2p8affineqb in getArithmeticInstrCost()
382 { ISD::SRA, MVT::v64i8, { 1, 6, 1, 2 } }, // gf2p8affineqb in getArithmeticInstrCost()
394 { ISD::SRA, MVT::v16i8, { 1, 8, 4, 5 } }, // psrlw, pand, pxor, psubb. in getArithmeticInstrCost()
397 { ISD::SRA, MVT::v32i8, { 1, 9, 4, 5 } }, // psrlw, pand, pxor, psubb. in getArithmeticInstrCost()
400 { ISD::SRA, MVT::v64i8, { 1, 9, 4, 6 } }, // psrlw, pand, pxor, psubb. in getArithmeticInstrCost()
404 { ISD::SRA, MVT::v16i16, { 1, 1, 1, 1 } }, // psrlw in getArithmeticInstrCost()
407 { ISD::SRA, MVT::v32i16, { 1, 1, 1, 1 } }, // psrlw in getArithmeticInstrCost()
419 { ISD::SRA, MVT::v64i8, { 3, 10, 12, 12 } }, // psrlw, pand, pxor, psubb. in getArithmeticInstrCost()
423 { ISD::SRA, MVT::v16i16, { 2, 7, 4, 4 } }, // psraw + split. in getArithmeticInstrCost()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/ |
| H A D | XtensaISelDAGToDAG.cpp | 186 case ISD::SRA: { in Select()
194 SDNode *SRA = in Select() local
195 CurDAG->getMachineNode(Xtensa::SRA, DL, VT, N0, SDValue(SSR, 0)); in Select()
196 ReplaceNode(Node, SRA); in Select()
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| /freebsd/contrib/telnet/libtelnet/ |
| H A D | auth-proto.h | 98 #ifdef SRA
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| H A D | auth.c | 165 #ifdef SRA
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| H A D | sra.c | 31 #ifdef SRA
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| /freebsd/crypto/heimdal/appl/telnet/libtelnet/ |
| H A D | auth-proto.h | 91 #ifdef SRA
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| H A D | auth.c | 119 #ifdef SRA
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMSelectionDAGInfo.h | 28 case ISD::SRA: return ARM_AM::asr; in getShiftOpcForNode()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZSelectionDAGInfo.cpp | 177 SDValue SRA = DAG.getNode(ISD::SRA, DL, MVT::i32, SHL, in addIPMSequence() local
179 return SRA; in addIPMSequence()
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| H A D | SystemZShortenInst.cpp | 367 TwoOperandOpcode == SystemZ::SRA) { in processBlock()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 84 setOperationAction(ISD::SRA, MVT::i8, Custom); in AVRTargetLowering()
87 setOperationAction(ISD::SRA, MVT::i16, Custom); in AVRTargetLowering()
90 setOperationAction(ISD::SRA, MVT::i32, Custom); in AVRTargetLowering()
260 case ISD::SRA: in LowerShifts()
294 case ISD::SRA: in LowerShifts()
304 case ISD::SRA: in LowerShifts()
350 } else if (Op.getOpcode() == ISD::SRA && ShiftAmount == 6) { in LowerShifts()
355 } else if (Op.getOpcode() == ISD::SRA && ShiftAmount == 7) { in LowerShifts()
385 if (Op.getOpcode() == ISD::SRA) in LowerShifts()
437 case ISD::SRA: in LowerShifts()
[all …]
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| /freebsd/crypto/openssl/test/ |
| H A D | testmldsa65.pem | 39 KE5+mIY+NnSHhMy2gnHe/fClylH9ChgLsR5cHOWhx9WuQgqEjuZv9MMjUsPx/SRA
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| /freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/RISCV/ |
| H A D | RISCVInstructions.h | 134 R_TYPE_INST(SRA);
277 SLTIU, XORI, ORI, ANDI, ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND,
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeIntegerTypes.cpp | 115 case ISD::SRA: in PromoteIntegerResult()
1136 ShiftOp = ISD::SRA; in PromoteIntRes_ADDSUBSHLSAT()
1198 unsigned ShiftOp = Signed ? ISD::SRA : ISD::SRL; in PromoteIntRes_MULFIX()
1300 Res = DAG.getNode(Signed ? ISD::SRA : ISD::SRL, dl, PromotedType, Res, in PromoteIntRes_DIVFIX()
2025 case ISD::SRA: in PromoteIntegerOperand()
3074 case ISD::SRA: in ExpandIntegerResult()
3228 assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); in ExpandShiftByConstant()
3230 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH, in ExpandShiftByConstant()
3233 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH, in ExpandShiftByConstant()
3235 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, in ExpandShiftByConstant()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 74 setOperationAction(ISD::SRA, MVT::i8, Custom); in MSP430TargetLowering()
77 setOperationAction(ISD::SRA, MVT::i16, Custom); in MSP430TargetLowering()
223 case ISD::SRA: return LowerShifts(Op, DAG); in LowerOperation()
862 case ISD::SRA: in LowerShifts()
866 Victim = (Opc == ISD::SRA) in LowerShifts()
1079 SR = DAG.getNode(ISD::SRA, dl, MVT::i16, SR, One); in LowerSETCC()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VVPNodes.def | 102 ADD_BINARY_VVP_OP(VVP_SRA,VP_SRA,SRA) REGISTER_PACKED(VVP_SRA)
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/ |
| H A D | LanaiMCCodeEmitter.cpp | 243 case LPAC::SRA: in getRrMemoryOpValue()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 757 SRA, enumerator
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsExpandPseudo.cpp | 185 BuildMI(sinkMBB, DL, TII->get(Mips::SRA), Dest) in expandAtomicCmpSwapSubword()
511 const unsigned SROp = IsUnsigned ? Mips::SRL : Mips::SRA; in expandAtomicBinOpSubword()
686 BuildMI(sinkMBB, DL, TII->get(Mips::SRA), Dest) in expandAtomicBinOpSubword()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelDAGToDAG.cpp | 169 case ISD::SRA: in Select()
1728 if (LHS.getOpcode() == ISD::SRL || LHS.getOpcode() == ISD::SRA) { in tryBFE()
1758 } else if (N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) { in tryBFE()
1816 if (N->getOpcode() == ISD::SRA) in tryBFE()
1861 if (N->getOpcode() == ISD::SRA) { in tryBFE()
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/ |
| H A D | CodeGenSchedule.cpp | 1860 for (const Record *SRA : in collectProcResources() local
1862 if (SRA->getValueInit("SchedModel")->isComplete()) { in collectProcResources()
1863 const Record *ModelDef = SRA->getValueAsDef("SchedModel"); in collectProcResources()
1864 addReadAdvance(SRA, getProcModel(ModelDef)); in collectProcResources()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 525 ISD::SRA, ISD::SRL, ISD::ROTL, in AMDGPUTargetLowering()
627 ISD::SRA, ISD::SRL, in AMDGPUTargetLowering()
1045 case ISD::SRA: in isNarrowingProfitable()
1085 assert((N->getOpcode() == ISD::SHL || N->getOpcode() == ISD::SRA || in isDesirableToCommuteWithShift()
1105 (N->user_begin()->getOpcode() == ISD::SRA || in isDesirableToCommuteWithShift()
1995 jq = DAG.getNode(ISD::SRA, DL, VT, jq, in LowerDIVREM24()
2489 SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp); in LowerFTRUNC()
3322 ISD::SRA, SL, MVT::i32, DAG.getNode(ISD::XOR, SL, MVT::i32, Lo, Hi), in LowerINT_TO_FP32()
3338 Sign = DAG.getNode(ISD::SRA, SL, MVT::i64, Src, in LowerINT_TO_FP32()
3530 Sign = DAG.getNode(ISD::SRA, SL, MVT::i32, in LowerFP_TO_INT64()
[all …]
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