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Searched refs:SPR (Results 1 – 25 of 25) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrVFP.td159 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr),
161 [(set SPR:$Sd, (alignedload32 addrmode5:$addr))]>,
194 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr),
196 [(alignedstore32 SPR:$Sd, addrmode5:$addr)]>,
434 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
436 [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]>,
459 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
461 [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]>,
484 (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
486 [(set SPR:$Sd, (fdiv SPR:$Sn, SPR:$Sm))]>,
[all …]
H A DARMInstrCDE.td487 def cde_vcx_s_regs : CDE_VCX_RegisterOperandsTemplate<SPR>;
550 def : Pat<(f32 (int_arm_cde_vcx1a timm:$coproc, (f32 SPR:$acc), timm:$imm)),
551 (f32 (CDE_VCX1A_fpsp p_imm:$coproc, SPR:$acc, imm_11b:$imm))>;
557 def : Pat<(f32 (int_arm_cde_vcx2 timm:$coproc, (f32 SPR:$n), timm:$imm)),
558 (f32 (CDE_VCX2_fpsp p_imm:$coproc, SPR:$n, imm_6b:$imm))>;
559 def : Pat<(f32 (int_arm_cde_vcx2a timm:$coproc, (f32 SPR:$acc), (f32 SPR:$n),
561 (f32 (CDE_VCX2A_fpsp p_imm:$coproc, SPR:$acc, SPR:$n, imm_6b:$imm))>;
568 def : Pat<(f32 (int_arm_cde_vcx3 timm:$coproc, (f32 SPR:$n), (f32 SPR:$m),
570 (f32 (CDE_VCX3_fpsp p_imm:$coproc, (f32 SPR:$n), (f32 SPR:$m),
572 def : Pat<(f32 (int_arm_cde_vcx3a timm:$coproc, (f32 SPR:$acc), (f32 SPR:$n),
[all …]
H A DARMRegisterInfo.td422 def SPR : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 31)> {
423 let AltOrders = [(add (decimate SPR, 2), SPR),
424 (add (decimate SPR, 4),
425 (decimate SPR, 2),
426 (decimate (rotl SPR, 1), 4),
427 (decimate (rotl SPR, 1), 2))];
435 let AltOrders = [(add (decimate HPR, 2), SPR),
446 // Subset of SPR which can be used as a source of NEON scalars for 16-bit
471 def FPWithVPR : RegisterClass<"ARM", [f32], 32, (add SPR, DPR, VPR)> {
476 // 32-bit SPR subregs).
[all …]
H A DARMRegisterBanks.td13 def FPRRegBank : RegisterBank<"FPRB", [HPR, SPR, DPR, QPR]>;
H A DARMInstrNEON.td4377 def : Pat<(v2f32 (fmul DPR:$Rn, (ARMvdup (f32 SPR:$Rm)))),
4379 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$Rm, ssub_0),
4385 def : Pat<(v4f32 (fmul QPR:$Rn, (ARMvdup (f32 SPR:$Rm)))),
4387 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$Rm, ssub_0),
5257 (ins SPR:$Vn, SPR_8:$Vm, VectorIndex32:$idx),
5278 def VFMALD : N3VCP8F16Q0<"vfmal", DPR, SPR, SPR, 0b00, 0b10, 1>;
5279 def VFMSLD : N3VCP8F16Q0<"vfmsl", DPR, SPR, SPR, 0b01, 0b10, 1>;
6585 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
6587 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
6588 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
[all …]
H A DARMInstrMVE.td881 f32, SPR>;
1904 (COPY_TO_REGCLASS (f32 (EXTRACT_SUBREG MQPR:$src, (SSubReg_f32_reg imm:$lane))), SPR)>;
1905 def : Pat<(insertelt (v4f32 MQPR:$src1), (f32 SPR:$src2), imm:$lane),
1906 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS MQPR:$src1, MQPR)), SPR:$src2, (SSubReg_f32_reg imm:$lane))>;
1914 (COPY_TO_REGCLASS HPR:$src2, SPR)),
1928 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
1929 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
H A DARMInstrInfo.td6545 def PseudoARMInitUndefSPR : PseudoInst<(outs SPR:$sd), (ins), NoItinerary, []>;
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.td54 // SPR - One of the 32-bit special-purpose registers
55 class SPR<bits<10> num, string n> : PPCReg<n> {
291 def LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>;
292 def LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]> {
297 def CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>;
298 def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]> {
303 def VRSAVE: SPR<256, "vrsave">, DwarfRegNum<[109]>;
306 def SPEFSCR: SPR<512, "spefscr">, DwarfRegNum<[612, 112]>;
308 def XER: SPR<1, "xer">, DwarfRegNum<[76]>;
311 // (which really is SPR register 1); this is the only bit interesting to a
[all …]
H A DPPCInstrFormats.td1693 bits<10> SPR;
1696 let Inst{11} = SPR{4};
1697 let Inst{12} = SPR{3};
1698 let Inst{13} = SPR{2};
1699 let Inst{14} = SPR{1};
1700 let Inst{15} = SPR{0};
1701 let Inst{16} = SPR{9};
1702 let Inst{17} = SPR{8};
1703 let Inst{18} = SPR{7};
1704 let Inst{19} = SPR{
[all...]
H A DPPCInstr64Bit.td530 def MFSPR8 : XFXForm_1<31, 339, (outs g8rc:$RST), (ins i32imm:$SPR),
531 "mfspr $RST, $SPR", IIC_SprMFSPR>;
532 def MTSPR8 : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, g8rc:$RST),
533 "mtspr $SPR, $RST", IIC_SprMTSPR>;
537 // 64-bit SPR manipulation instrs.
2021 def : Pat<(i64 (int_ppc_mfspr timm:$SPR)),
2022 (MFSPR8 $SPR)>;
2023 def : Pat<(int_ppc_mtspr timm:$SPR, g8rc:$RT),
2024 (MTSPR8 $SPR, $RT)>;
H A DPPCInstrInfo.td2678 def MFSPR : XFXForm_1<31, 339, (outs gprc:$RST), (ins i32imm:$SPR),
2679 "mfspr $RST, $SPR", IIC_SprMFSPR>;
2680 def MTSPR : XFXForm_1<31, 467, (outs), (ins i32imm:$SPR, gprc:$RST),
2681 "mtspr $SPR, $RST", IIC_SprMTSPR>;
2683 def MFTB : XFXForm_1<31, 371, (outs gprc:$RST), (ins i32imm:$SPR),
2684 "mftb $RST, $SPR", IIC_SprMFTB>;
2686 def MFPMR : XFXForm_1<31, 334, (outs gprc:$RST), (ins i32imm:$SPR),
2687 "mfpmr $RST, $SPR", IIC_SprMFPMR>;
2689 def MTPMR : XFXForm_1<31, 462, (outs), (ins i32imm:$SPR, gprc:$RST),
2690 "mtpmr $SPR, $RST", IIC_SprMTPMR>;
[all …]
H A DPPC.td229 "Target supports move to SPR with branch fusion",
H A DP9InstrResources.td937 (instregex "MF(SPR|CTR|LR)(8)?$"),
/freebsd/sys/contrib/device-tree/Bindings/powerpc/opal/
H A Dpower-mgt.txt55 0x00800000 /* This state uses SPR PMICR instruction */
110 state if the flag indicates that pmicr SPR should be set. This
/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dtlv320aic31xx.txt46 * SPR, devices with stereo speaker amp
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86PartialReduction.cpp236 auto SPR = matchSelectPattern(SI, LHS, RHS); in trySADReplacement() local
237 if (SPR.Flavor != SPF_ABS) in trySADReplacement()
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mn-bsh-smm-s2pro.dts29 "Ext Spk", "SPR";
/freebsd/contrib/llvm-project/llvm/lib/Analysis/
H A DLazyValueInfo.cpp864 SelectPatternResult SPR = matchSelectPattern(SI, LHS, RHS); in solveBlockValueSelect() local
867 if (SelectPatternResult::isMinOrMax(SPR.Flavor) && in solveBlockValueSelect()
871 switch (SPR.Flavor) { in solveBlockValueSelect()
889 if (SPR.Flavor == SPF_ABS) { in solveBlockValueSelect()
898 if (SPR.Flavor == SPF_NABS) { in solveBlockValueSelect()
H A DValueTracking.cpp8287 SelectPatternResult SPR = matchClamp(Pred, CmpLHS, CmpRHS, TrueVal, FalseVal); in matchMinMax() local
8288 if (SPR.Flavor != SelectPatternFlavor::SPF_UNKNOWN) in matchMinMax()
8289 return SPR; in matchMinMax()
8291 SPR = matchMinMaxOfMinMax(Pred, CmpLHS, CmpRHS, TrueVal, FalseVal, Depth); in matchMinMax()
8292 if (SPR.Flavor != SelectPatternFlavor::SPF_UNKNOWN) in matchMinMax()
8293 return SPR; in matchMinMax()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineSelect.cpp3794 SelectPatternResult SPR = matchSelectPattern(&SI, LHS, RHS, &CastOp); in visitSelectInst() local
3795 auto SPF = SPR.Flavor; in visitSelectInst()
3820 CmpInst::Predicate MinMaxPred = getMinMaxPred(SPF, SPR.Ordered); in visitSelectInst()
H A DInstCombineCompares.cpp7372 SelectPatternResult SPR = matchSelectPattern(SI, A, B); in visitICmpInst() local
7373 if (SPR.Flavor != SPF_UNKNOWN) in visitICmpInst()
8133 SelectPatternResult SPR = matchSelectPattern(SI, A, B); in visitFCmpInst() local
8134 if (SPR.Flavor != SPF_UNKNOWN) in visitFCmpInst()
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Dam43x-epos-evm.dts116 "Speaker", "SPR";
/freebsd/contrib/file/magic/Magdir/
H A Ddatabase682 # Foxpro Generated Screen Program *.SPR
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.cpp3734 auto SPR = matchSelectPattern(const_cast<User*>(&I), LHS, RHS); in visitSelect() local
3736 switch (SPR.Flavor) { in visitSelect()
3742 switch (SPR.NaNBehavior) { in visitSelect()
3755 switch (SPR.NaNBehavior) { in visitSelect()
/freebsd/contrib/one-true-awk/testdir/
H A Dfunstack.in3779 …SPR) procedure does not test all the features of a pattern at once. Instead, it selects a feature …
19497 @Article{Stockman:1976:SPR,