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Searched refs:SPLAT_VECTOR (Results 1 – 23 of 23) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp136 setOperationAction(ISD::SPLAT_VECTOR, T, Legal); in initializeHVXLowering()
137 setOperationAction(ISD::SPLAT_VECTOR, T, Legal); in initializeHVXLowering()
152 setOperationAction(ISD::SPLAT_VECTOR, MVT::f16, Custom); in initializeHVXLowering()
206 setOperationAction(ISD::SPLAT_VECTOR, T, Legal); in initializeHVXLowering()
286 setOperationAction(ISD::SPLAT_VECTOR, T, Custom); in initializeHVXLowering()
835 SDValue S = DAG.getNode(ISD::SPLAT_VECTOR, dl, WordTy, SplatV); in buildHvxVectorReg()
943 SDValue SplatV = DAG.getNode(ISD::SPLAT_VECTOR, dl, VecTy, Words[n]); in buildHvxVectorReg()
1502 SDValue True = DAG.getNode(ISD::SPLAT_VECTOR, dl, ResTy, in extendHvxVectorPred()
1656 SDValue Splat = DAG.getNode(ISD::SPLAT_VECTOR, dl, SplatTy, ToInt32); in LowerHvxSplatVector()
1880 SDValue Vec1 = DAG.getNode(ISD::SPLAT_VECTOR, d in LowerHvxCttz()
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H A DHexagonISelLowering.cpp1666 ISD::SPLAT_VECTOR, in HexagonTargetLowering()
1725 setOperationAction(ISD::SPLAT_VECTOR, NativeVT, Legal); in HexagonTargetLowering()
2384 case ISD::SPLAT_VECTOR: in getSplatValue()
2580 // Legalize the operand of SPLAT_VECTOR. in buildVector32()
2582 return DAG.getNode(ISD::SPLAT_VECTOR, dl, VecTy, Ext); in buildVector32()
2641 // Legalize the operand of SPLAT_VECTOR in buildVector64()
2645 return DAG.getNode(ISD::SPLAT_VECTOR, dl, VecTy, Ext); in buildVector64()
2889 return DAG.getNode(ISD::SPLAT_VECTOR, dl, Ty, getZero(dl, MVT::i32, DAG)); in getZero()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h641 SPLAT_VECTOR, enumerator
H A DSelectionDAG.h883 return getNode(ISD::SPLAT_VECTOR, DL, VT, Op);
H A DTargetLowering.h4208 return Op.getOpcode() == ISD::SPLAT_VECTOR || in isTargetCanonicalConstantNode()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp146 if (N->getOpcode() == ISD::SPLAT_VECTOR) { in isConstantSplatVector()
185 if (!BuildVectorOnly && N->getOpcode() == ISD::SPLAT_VECTOR) { in isConstantSplatVectorAllOnes()
234 if (!BuildVectorOnly && N->getOpcode() == ISD::SPLAT_VECTOR) { in isConstantSplatVectorAllZeros()
365 ISD::SPLAT_VECTOR != Op.getOpcode()) in matchUnaryPredicateImpl()
403 LHS.getOpcode() != ISD::SPLAT_VECTOR)) in matchBinaryPredicate()
1674 TLI->isOperationLegal(ISD::SPLAT_VECTOR, VT)) { in getConstant()
2760 case ISD::SPLAT_VECTOR: in isSplatValue()
2974 case ISD::SPLAT_VECTOR: in getSplatSourceVector()
3176 case ISD::SPLAT_VECTOR: { in computeKnownBits()
4392 if (Val.getOpcode() == ISD::SPLAT_VECTOR) in isKnownToBeAPowerOfTwo()
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H A DSelectionDAGDumper.cpp334 case ISD::SPLAT_VECTOR: return "splat_vector"; in getOperationName()
H A DLegalizeVectorOps.cpp1169 : ISD::SPLAT_VECTOR, in ExpandSELECT()
1516 !TLI.isOperationLegalOrCustom(ISD::SPLAT_VECTOR, EVLVecVT)))) in ExpandVP_MERGE()
H A DDAGCombiner.cpp1042 if (N.getOpcode() != ISD::BUILD_VECTOR && N.getOpcode() != ISD::SPLAT_VECTOR) in isConstantOrConstantVector()
10370 else if (N1.getOpcode() == ISD::SPLAT_VECTOR) { in visitSRA()
12459 OpRHS.getOpcode() == ISD::SPLAT_VECTOR) && in visitVSELECT()
12515 OpRHS.getOpcode() == ISD::SPLAT_VECTOR) { in visitVSELECT()
12517 CondRHS.getOpcode() == ISD::SPLAT_VECTOR) { in visitVSELECT()
15061 if (N0.getOpcode() == ISD::SPLAT_VECTOR && in visitTRUNCATE()
15063 (!LegalOperations || TLI.isOperationLegal(ISD::SPLAT_VECTOR, VT))) { in visitTRUNCATE()
22599 VecOp.getOpcode() == ISD::SPLAT_VECTOR) && in visitEXTRACT_VECTOR_ELT()
23825 if (TLI.getOperationAction(ISD::SPLAT_VECTOR, VT) != TargetLowering::Expand) in visitBUILD_VECTOR()
23828 return DAG.getNode(ISD::SPLAT_VECTOR, SDLoc(N), VT, V); in visitBUILD_VECTOR()
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H A DTargetLowering.cpp1188 case ISD::SPLAT_VECTOR: { in SimplifyDemandedBits()
6132 } else if (Op1.getOpcode() == ISD::SPLAT_VECTOR) { in BuildExactSDIV()
6195 } else if (Op1.getOpcode() == ISD::SPLAT_VECTOR) { in BuildExactUDIV()
6364 } else if (N1.getOpcode() == ISD::SPLAT_VECTOR) { in BuildSDIV()
6544 } else if (N1.getOpcode() == ISD::SPLAT_VECTOR) { in BuildUDIV()
6828 } else if (D.getOpcode() == ISD::SPLAT_VECTOR) { in prepareUREMEqFold()
7104 } else if (D.getOpcode() == ISD::SPLAT_VECTOR) { in prepareSREMEqFold()
H A DLegalizeVectorTypes.cpp1093 case ISD::SPLAT_VECTOR: in SplitVectorResult()
1998 StartOfHi = DAG.getNode(ISD::SPLAT_VECTOR, dl, HiVT, StartOfHi); in SplitVecRes_STEP_VECTOR()
2013 assert(N->getOpcode() == ISD::SPLAT_VECTOR && "Unexpected opcode");
4329 case ISD::SPLAT_VECTOR: in WidenVectorResult()
H A DLegalizeIntegerTypes.cpp141 case ISD::SPLAT_VECTOR: in PromoteIntegerResult()
1932 case ISD::SPLAT_VECTOR: in PromoteIntegerOperand()
5268 case ISD::SPLAT_VECTOR: Res = ExpandIntOp_SPLAT_VECTOR(N); break; in ExpandIntegerOperand()
H A DLegalizeDAG.cpp4276 case ISD::SPLAT_VECTOR: in ExpandNode()
5788 case ISD::SPLAT_VECTOR: { in PromoteNode()
H A DSelectionDAGBuilder.cpp4022 setValue(&I, DAG.getNode(ISD::SPLAT_VECTOR, DL, VT, FirstElt)); in visitShuffleVector()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp286 case ISD::SPLAT_VECTOR: in isZeroingInactiveLanes()
1422 setOperationAction(ISD::SPLAT_VECTOR, VT, Custom); in AArch64TargetLowering()
1445 setOperationAction(ISD::SPLAT_VECTOR, VT, Legal); in AArch64TargetLowering()
1586 setOperationAction(ISD::SPLAT_VECTOR, VT, Legal); in AArch64TargetLowering()
1663 setOperationAction(ISD::SPLAT_VECTOR, VT, Legal); in AArch64TargetLowering()
2096 setOperationAction(ISD::SPLAT_VECTOR, VT, Default); in addTypeForFixedLengthSVE()
6866 case ISD::SPLAT_VECTOR: in LowerOperation()
10721 SDValue SplatPred = DAG.getNode(ISD::SPLAT_VECTOR, DL, PredVT, CCVal); in LowerSELECT()
10732 SDValue SplatPred = DAG.getNode(ISD::SPLAT_VECTOR, DL, PredVT, SplatVal); in LowerSELECT()
13373 SDValue SplatOne = DAG.getNode(ISD::SPLAT_VECTOR, DL, MVT::nxv2i64, One); in LowerDUPQLane()
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H A DAArch64ISelDAGToDAG.cpp211 case ISD::SPLAT_VECTOR: { in SelectDupZeroOrUndef()
229 case ISD::SPLAT_VECTOR: { in SelectDupZero()
245 case ISD::SPLAT_VECTOR: { in SelectDupNegativeZero()
285 if (N->getOpcode() != ISD::SPLAT_VECTOR) in SelectSVEShiftSplatImmR()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp749 setOperationAction(ISD::SPLAT_VECTOR, VT, Custom); in RISCVTargetLowering()
819 setOperationAction(ISD::SPLAT_VECTOR, VT, Legal); in RISCVTargetLowering()
969 setOperationAction(ISD::SPLAT_VECTOR, VT, Legal); in RISCVTargetLowering()
1077 setOperationAction(ISD::SPLAT_VECTOR, VT, Custom); in RISCVTargetLowering()
1108 setOperationAction(ISD::SPLAT_VECTOR, VT, Custom); in RISCVTargetLowering()
1215 // Make SPLAT_VECTOR Legal so DAGCombine will convert splat vectors to in RISCVTargetLowering()
1218 // FIXME: Use SPLAT_VECTOR for all types? DAGCombine probably needs in RISCVTargetLowering()
1221 setOperationAction(ISD::SPLAT_VECTOR, VT, Legal); in RISCVTargetLowering()
1326 // FIXME: We should prefer BUILD_VECTOR over SPLAT_VECTOR. in RISCVTargetLowering()
1327 setOperationAction(ISD::SPLAT_VECTOR, V in RISCVTargetLowering()
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H A DRISCVISelDAGToDAG.cpp60 case ISD::SPLAT_VECTOR: { in PreprocessISelDAG()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp771 ISD::SPLAT_VECTOR, ISD::LRINT, ISD::LLRINT, ISD::FTAN, ISD::FACOS, in initActions()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp219 setOperationAction(ISD::SPLAT_VECTOR, T, Legal); in WebAssemblyTargetLowering()
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td785 def splat_vector : SDNode<"ISD::SPLAT_VECTOR", SDTypeProfile<1, 1, []>, []>;
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp5191 if (N->getOpcode() == ISD::SPLAT_VECTOR) in isZeroVector()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp28321 Op->getOpcode() == ISD::SPLAT_VECTOR) { in LowerFMINIMUM_FMAXIMUM()