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Searched refs:SPLAT_VECTOR (Results 1 – 24 of 24) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp138 setOperationAction(ISD::SPLAT_VECTOR, T, Legal); in initializeHVXLowering()
139 setOperationAction(ISD::SPLAT_VECTOR, T, Legal); in initializeHVXLowering()
154 setOperationAction(ISD::SPLAT_VECTOR, MVT::f16, Custom); in initializeHVXLowering()
208 setOperationAction(ISD::SPLAT_VECTOR, T, Legal); in initializeHVXLowering()
290 setOperationAction(ISD::SPLAT_VECTOR, T, Custom); in initializeHVXLowering()
845 SDValue S = DAG.getNode(ISD::SPLAT_VECTOR, dl, WordTy, SplatV); in buildHvxVectorReg()
953 SDValue SplatV = DAG.getNode(ISD::SPLAT_VECTOR, dl, VecTy, Words[n]); in buildHvxVectorReg()
1517 SDValue True = DAG.getNode(ISD::SPLAT_VECTOR, dl, ResTy, in extendHvxVectorPred()
1672 SDValue Splat = DAG.getNode(ISD::SPLAT_VECTOR, dl, SplatTy, ToInt32); in LowerHvxSplatVector()
1895 SDValue Vec1 = DAG.getNode(ISD::SPLAT_VECTOR, dl, ResTy, in LowerHvxCttz()
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H A DHexagonISelLowering.cpp1736 ISD::SPLAT_VECTOR, in HexagonTargetLowering()
1799 setOperationAction(ISD::SPLAT_VECTOR, NativeVT, Legal); in HexagonTargetLowering()
2406 case ISD::SPLAT_VECTOR: in getSplatValue()
2604 return DAG.getNode(ISD::SPLAT_VECTOR, dl, VecTy, Ext); in buildVector32()
2667 return DAG.getNode(ISD::SPLAT_VECTOR, dl, VecTy, Ext); in buildVector64()
2911 return DAG.getNode(ISD::SPLAT_VECTOR, dl, Ty, getZero(dl, MVT::i32, DAG)); in getZero()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h663 SPLAT_VECTOR, enumerator
H A DSelectionDAG.h915 return getNode(ISD::SPLAT_VECTOR, DL, VT, Op);
H A DTargetLowering.h4370 return Op.getOpcode() == ISD::SPLAT_VECTOR || in isTargetCanonicalConstantNode()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp152 if (N->getOpcode() == ISD::SPLAT_VECTOR) { in isConstantSplatVector()
187 if (!BuildVectorOnly && N->getOpcode() == ISD::SPLAT_VECTOR) { in isConstantSplatVectorAllOnes()
233 if (!BuildVectorOnly && N->getOpcode() == ISD::SPLAT_VECTOR) { in isConstantSplatVectorAllZeros()
361 ISD::SPLAT_VECTOR != Op.getOpcode()) in matchUnaryPredicateImpl()
400 LHS.getOpcode() != ISD::SPLAT_VECTOR)) in matchBinaryPredicate()
1713 TLI->isOperationLegal(ISD::SPLAT_VECTOR, VT)) { in getConstant()
3003 case ISD::SPLAT_VECTOR: in isSplatValue()
3222 case ISD::SPLAT_VECTOR: in getSplatSourceVector()
3419 case ISD::SPLAT_VECTOR: { in computeKnownBits()
4663 if (Val.getOpcode() == ISD::SPLAT_VECTOR) in isKnownToBeAPowerOfTwo()
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H A DLegalizeTypesGeneric.cpp378 if (VecVT.isInteger() && TLI.isOperationLegal(ISD::SPLAT_VECTOR, VecVT) && in ExpandOp_BUILD_VECTOR()
H A DSelectionDAGDumper.cpp351 case ISD::SPLAT_VECTOR: return "splat_vector"; in getOperationName()
H A DLegalizeVectorOps.cpp1351 : ISD::SPLAT_VECTOR, in ExpandSELECT()
1686 !TLI.isOperationLegalOrCustom(ISD::SPLAT_VECTOR, EVLVecVT)))) in ExpandVP_MERGE()
H A DDAGCombiner.cpp1062 if (N.getOpcode() != ISD::BUILD_VECTOR && N.getOpcode() != ISD::SPLAT_VECTOR) in isConstantOrConstantVector()
10816 else if (N1.getOpcode() == ISD::SPLAT_VECTOR) { in visitSRA()
13321 OpRHS.getOpcode() == ISD::SPLAT_VECTOR) && in visitVSELECT()
13377 OpRHS.getOpcode() == ISD::SPLAT_VECTOR) { in visitVSELECT()
13379 CondRHS.getOpcode() == ISD::SPLAT_VECTOR) { in visitVSELECT()
16109 if (N0.getOpcode() == ISD::SPLAT_VECTOR && in visitTRUNCATE()
16111 (!LegalOperations || TLI.isOperationLegal(ISD::SPLAT_VECTOR, VT))) { in visitTRUNCATE()
23628 VecOp.getOpcode() == ISD::SPLAT_VECTOR) && in visitEXTRACT_VECTOR_ELT()
24905 if (TLI.getOperationAction(ISD::SPLAT_VECTOR, VT) != TargetLowering::Expand) in visitBUILD_VECTOR()
24908 return DAG.getNode(ISD::SPLAT_VECTOR, SDLoc(N), VT, V); in visitBUILD_VECTOR()
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H A DTargetLowering.cpp1243 case ISD::SPLAT_VECTOR: { in SimplifyDemandedBits()
6352 } else if (Op1.getOpcode() == ISD::SPLAT_VECTOR) { in BuildExactSDIV()
6413 } else if (Op1.getOpcode() == ISD::SPLAT_VECTOR) { in BuildExactUDIV()
6579 } else if (N1.getOpcode() == ISD::SPLAT_VECTOR) { in BuildSDIV()
6765 } else if (N1.getOpcode() == ISD::SPLAT_VECTOR) { in BuildUDIV()
7056 } else if (D.getOpcode() == ISD::SPLAT_VECTOR) { in prepareUREMEqFold()
7334 } else if (D.getOpcode() == ISD::SPLAT_VECTOR) { in prepareSREMEqFold()
H A DLegalizeVectorTypes.cpp1141 case ISD::SPLAT_VECTOR: in SplitVectorResult()
2073 StartOfHi = DAG.getNode(ISD::SPLAT_VECTOR, dl, HiVT, StartOfHi); in SplitVecRes_STEP_VECTOR()
2088 assert(N->getOpcode() == ISD::SPLAT_VECTOR && "Unexpected opcode"); in SplitVecRes_ScalarOp()
4689 case ISD::SPLAT_VECTOR: in WidenVectorResult()
H A DLegalizeIntegerTypes.cpp145 case ISD::SPLAT_VECTOR: in PromoteIntegerResult()
1980 case ISD::SPLAT_VECTOR: in PromoteIntegerOperand()
5507 case ISD::SPLAT_VECTOR: Res = ExpandIntOp_SPLAT_VECTOR(N); break; in ExpandIntegerOperand()
H A DSelectionDAGBuilder.cpp1803 ISD::SPLAT_VECTOR, DL, VT, in getValueImpl()
1918 ISD::SPLAT_VECTOR, getCurSDLoc(), in getValueImpl()
4082 setValue(&I, DAG.getNode(ISD::SPLAT_VECTOR, DL, VT, FirstElt)); in visitShuffleVector()
8208 SDValue Splat = DAG.getNode(ISD::SPLAT_VECTOR, sdl, Op1VT, Op2Elem); in visitIntrinsicCall()
H A DLegalizeDAG.cpp4414 case ISD::SPLAT_VECTOR: in ExpandNode()
6048 case ISD::SPLAT_VECTOR: { in PromoteNode()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp293 case ISD::SPLAT_VECTOR: in isZeroingInactiveLanes()
1503 setOperationAction(ISD::SPLAT_VECTOR, VT, Custom); in AArch64TargetLowering()
1537 setOperationAction(ISD::SPLAT_VECTOR, VT, Legal); in AArch64TargetLowering()
1680 setOperationAction(ISD::SPLAT_VECTOR, VT, Legal); in AArch64TargetLowering()
1763 setOperationAction(ISD::SPLAT_VECTOR, VT, Legal); in AArch64TargetLowering()
2333 setOperationAction(ISD::SPLAT_VECTOR, VT, Default); in addTypeForFixedLengthSVE()
7334 case ISD::SPLAT_VECTOR: in LowerOperation()
11549 SDValue SplatPred = DAG.getNode(ISD::SPLAT_VECTOR, DL, PredVT, CCVal); in LowerSELECT()
11560 SDValue SplatPred = DAG.getNode(ISD::SPLAT_VECTOR, DL, PredVT, SplatVal); in LowerSELECT()
14223 SDValue SplatOne = DAG.getNode(ISD::SPLAT_VECTOR, DL, MVT::nxv2i64, One); in LowerDUPQLane()
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H A DAArch64ISelDAGToDAG.cpp216 case ISD::SPLAT_VECTOR: { in SelectDupZeroOrUndef()
236 case ISD::SPLAT_VECTOR: { in SelectDupZero()
280 if (N->getOpcode() != ISD::SPLAT_VECTOR) in SelectSVEShiftSplatImmR()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp796 setOperationAction(ISD::SPLAT_VECTOR, VT, Custom); in RISCVTargetLowering()
867 setOperationAction(ISD::SPLAT_VECTOR, VT, Legal); in RISCVTargetLowering()
1065 setOperationAction(ISD::SPLAT_VECTOR, VT, Legal); in RISCVTargetLowering()
1169 setOperationAction({ISD::SPLAT_VECTOR, ISD::EXPERIMENTAL_VP_SPLAT, in RISCVTargetLowering()
1173 setOperationAction({ISD::SPLAT_VECTOR, ISD::EXPERIMENTAL_VP_SPLAT}, in RISCVTargetLowering()
1337 setOperationAction(ISD::SPLAT_VECTOR, VT, Legal); in RISCVTargetLowering()
1652 ISD::SPLAT_VECTOR, ISD::BUILD_VECTOR, ISD::CONCAT_VECTORS, in RISCVTargetLowering()
7819 case ISD::SPLAT_VECTOR: { in LowerOperation()
7834 DAG.getNode(ISD::SPLAT_VECTOR, DL, IVT, Elt)); in LowerOperation()
13381 if (Vec.getOpcode() == ISD::SPLAT_VECTOR || in lowerVPSpliceExperimental()
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H A DRISCVISelDAGToDAG.cpp52 case ISD::SPLAT_VECTOR: { in PreprocessISelDAG()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp868 ISD::ZERO_EXTEND_VECTOR_INREG, ISD::SPLAT_VECTOR, in initActions()
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td830 def splat_vector : SDNode<"ISD::SPLAT_VECTOR", SDTypeProfile<1, 1, []>, []>;
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp243 setOperationAction(ISD::SPLAT_VECTOR, T, Legal); in WebAssemblyTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp5775 if (N->getOpcode() == ISD::SPLAT_VECTOR) in isZeroVector()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp29359 Op->getOpcode() == ISD::SPLAT_VECTOR) { in LowerFMINIMUM_FMAXIMUM()