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Searched refs:SMAX (Results 1 – 25 of 40) sorted by relevance

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/freebsd/contrib/ntp/ntpd/
H A Drefclock_as2201.c65 #define SMAX 200 /* statistics buffer length */ macro
79 char stats[SMAX]; /* statistics buffer */
267 if ((int)(up->lastptr - up->stats + pp->lencode) > SMAX - 2) in as2201_receive()
331 if ((int)(up->lastptr - up->stats + pp->lencode) > SMAX - 2) in as2201_receive()
337 if ((int)(up->lastptr - up->stats + 1 + octets) > SMAX - 2) in as2201_receive()
H A Drefclock_hpgps.c100 #define SMAX 23*80+1 /* for :SYSTEM:PRINT? status screen response */ macro
122 char statscrn[SMAX]; /* receiver status screen buffer */
302 if ((int)(pp->lencode + 2) <= (SMAX - (up->lastptr - up->statscrn))) { in hpgps_receive()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVVPNodes.def85 HELPER_REDUCTION(SMAX, SMAX)
H A DVEISelLowering.cpp206 setOperationAction(ISD::SMAX, IntVT, Legal); in initSPUActions()
2908 case ISD::SMAX: in isI32Insn()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp3595 { ISD::SMAX, MVT::v32i16, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3596 { ISD::SMAX, MVT::v64i8, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3657 { ISD::SMAX, MVT::v8i64, { 1, 3, 1, 1 } }, in getIntrinsicInstrCost()
3658 { ISD::SMAX, MVT::v16i32, { 1, 1, 1, 1 } }, in getIntrinsicInstrCost()
3659 { ISD::SMAX, MVT::v32i16, { 3, 7, 5, 5 } }, in getIntrinsicInstrCost()
3660 { ISD::SMAX, MVT::v64i8, { 3, 7, 5, 5 } }, in getIntrinsicInstrCost()
3661 { ISD::SMAX, MVT::v4i64, { 1, 3, 1, 1 } }, in getIntrinsicInstrCost()
3662 { ISD::SMAX, MVT::v2i64, { 1, 3, 1, 1 } }, in getIntrinsicInstrCost()
3802 { ISD::SMAX, MVT::v2i64, { 2, 7, 2, 3 } }, in getIntrinsicInstrCost()
3803 { ISD::SMAX, MVT::v4i64, { 2, 7, 2, 3 } }, in getIntrinsicInstrCost()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h697 SMAX, enumerator
H A DSDPatternMatch.h579 return BinaryOpc_match<LHS, RHS, true>(ISD::SMAX, L, R);
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeIntegerTypes.cpp104 case ISD::SMAX: Res = PromoteIntRes_SExtIntBinOp(N); break; in PromoteIntegerResult()
1119 Result = matcher.getNode(ISD::SMAX, dl, PromotedType, Result, SatMin); in PromoteIntRes_ADDSUBSHLSAT()
1183 V = DAG.getNode(ISD::SMAX, dl, VT, V, in SaturateWidenedDIVFIX()
1780 !TLI.isOperationLegal(ISD::SMAX, NVT)) { in PromoteIntRes_ABS()
2868 case ISD::SMAX: in ExpandIntegerResult()
3244 case ISD::SMAX: in getExpandedMinMaxOps()
3281 if ((N->getOpcode() == ISD::SMAX && isNullConstant(RHS)) || in ExpandIntRes_MINMAX()
3340 case ISD::SMAX: in ExpandIntRes_MINMAX()
H A DSelectionDAG.cpp456 return ISD::SMAX; in getVecReduceBaseOpcode()
4086 case ISD::SMAX: { in computeKnownBits()
4089 bool IsMax = (Opcode == ISD::SMAX); in computeKnownBits()
4092 if (Op.getOperand(0).getOpcode() == (IsMax ? ISD::SMIN : ISD::SMAX)) in computeKnownBits()
4403 if (Val.getOpcode() == ISD::SMIN || Val.getOpcode() == ISD::SMAX || in isKnownToBeAPowerOfTwo()
4675 case ISD::SMAX: { in ComputeNumSignBits()
4678 bool IsMax = (Opcode == ISD::SMAX); in ComputeNumSignBits()
4681 if (Op.getOperand(0).getOpcode() == (IsMax ? ISD::SMIN : ISD::SMAX)) in ComputeNumSignBits()
5264 case ISD::SMAX: in canCreateUndefOrPoison()
5562 case ISD::SMAX: { in isKnownNeverZero()
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H A DSelectionDAGDumper.cpp305 case ISD::SMAX: return "smax"; in getOperationName()
H A DLegalizeVectorOps.cpp436 case ISD::SMAX: in LegalizeOp()
1020 case ISD::SMAX: in Expand()
H A DLegalizeDAG.cpp2481 SDValue ClampN_Small = DAG.getNode(ISD::SMAX, dl, ExpVT, N, ClampMinVal); in expandLdexp()
3614 case ISD::SMAX: in ExpandNode()
3621 case ISD::SMAX: Pred = ISD::SETGT; break; in ExpandNode()
5233 case ISD::SMAX: in PromoteNode()
5253 case ISD::SMAX: in PromoteNode()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedA64FX.td2138 (instregex "^(AND|EOR|OR|SADD|SMAX|SMIN|UADD|UMAX|UMIN)V_VPZ_B")>;
2146 (instregex "^(AND|EOR|OR|SADD|SMAX|SMIN|UADD|UMAX|UMIN)V_VPZ_H")>;
2154 (instregex "^(AND|EOR|OR|SADD|SMAX|SMIN|UADD|UMAX|UMIN)V_VPZ_S")>;
2162 (instregex "^(AND|EOR|OR|SADD|SMAX|SMIN|UADD|UMAX|UMIN)V_VPZ_D")>;
H A DAArch64ISelLowering.cpp662 setOperationAction(ISD::SMAX, MVT::i32, Legal); in AArch64TargetLowering()
663 setOperationAction(ISD::SMAX, MVT::i64, Legal); in AArch64TargetLowering()
1259 setOperationAction(ISD::SMAX, VT, Custom); in AArch64TargetLowering()
1453 setOperationAction(ISD::SMAX, VT, Custom); in AArch64TargetLowering()
1718 setOperationAction(ISD::SMAX, MVT::v1i64, Custom); in AArch64TargetLowering()
1719 setOperationAction(ISD::SMAX, MVT::v2i64, Custom); in AArch64TargetLowering()
1904 for (unsigned Opcode : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}) in addTypeForNEON()
2094 setOperationAction(ISD::SMAX, VT, Default); in addTypeForFixedLengthSVE()
4555 Sat = DAG.getNode(ISD::SMAX, DL, IntVT, Min, MaxC); in LowerVectorFP_TO_INT_SAT()
4612 Sat = DAG.getNode(ISD::SMAX, DL, DstVT, Min, MaxC); in LowerFP_TO_INT_SAT()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp121 setOperationAction(ISD::SMAX, MVT::i32, Legal); in ARCTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp378 setOperationAction({ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}, XLenVT, in RISCVTargetLowering()
381 setOperationAction({ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}, MVT::i32, in RISCVTargetLowering()
829 setOperationAction({ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}, VT, in RISCVTargetLowering()
1240 {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX, ISD::ABS}, VT, Custom); in RISCVTargetLowering()
1456 setOperationAction(ISD::SMAX, XLenVT, Legal); in RISCVTargetLowering()
1479 setTargetDAGCombine({ISD::UMAX, ISD::UMIN, ISD::SMAX, ISD::SMIN}); in RISCVTargetLowering()
5702 Result = DAG.getNode(ISD::SMAX, DL, MVT::i64, Result, SatMin); in lowerSADDSAT_SSUBSAT()
5990 OP_CASE(SMAX) in getRISCVVLOp()
6013 VP_CASE(SMAX) // VP_SMAX in getRISCVVLOp()
7030 case ISD::SMAX: in LowerOperation()
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/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DVPIntrinsics.def221 VP_PROPERTY_FUNCTIONAL_SDOPC(SMAX)
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp465 case ISD::SMAX: in NVPTXTargetLowering()
531 ISD::SETCC, ISD::SHL, ISD::SINT_TO_FP, ISD::SMAX, in NVPTXTargetLowering()
674 setOperationAction(ISD::SMAX, Ty, Legal); in NVPTXTargetLowering()
684 setI16x2OperationAction(ISD::SMAX, MVT::v2i16, Legal, Custom); in NVPTXTargetLowering()
2800 case ISD::SMAX: in LowerOperation()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp552 setOperationAction({ISD::Constant, ISD::SMIN, ISD::SMAX, ISD::UMIN, in SITargetLowering()
775 ISD::SRA, ISD::SMIN, ISD::UMIN, ISD::SMAX, ISD::UMAX, in SITargetLowering()
794 ISD::MUL, ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, in SITargetLowering()
907 ISD::SMAX, in SITargetLowering()
5849 case ISD::SMAX: in LowerOperation()
6730 SDValue ClampMin = DAG.getNode(ISD::SMAX, DL, ExpVT, Exp, MinExp); in lowerFLDEXP()
13028 case ISD::SMAX: in minMaxOpcToMin3Max3Opc()
13162 case ISD::SMAX: in supportsMin3Max3()
13215 if (Opc == ISD::SMIN && Op0.getOpcode() == ISD::SMAX && Op0.hasOneUse()) { in performMinMaxCombine()
13220 if (Opc == ISD::SMAX && Op0.getOpcode() == ISD::SMIN && Op0.hasOneUse()) { in performMinMaxCombine()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp342 setOperationAction(ISD::SMAX, Ty, Legal); in addMSAIntType()
2004 return DAG.getNode(ISD::SMAX, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2016 return DAG.getNode(ISD::SMAX, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp214 setOperationAction(ISD::SMAX, T, Legal); in initializeHVXLowering()
319 setOperationAction(ISD::SMAX, T, Custom); in initializeHVXLowering()
3182 case ISD::SMAX: in LowerHvxOperation()
H A DHexagonISelLowering.cpp1560 {ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}) { in HexagonTargetLowering()
1733 setOperationAction(ISD::SMAX, VT, Legal); in HexagonTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp259 setOperationAction({ISD::UMAX, ISD::UMIN, ISD::SMAX, ISD::SMIN}, VT, in LoongArchTargetLowering()
306 setOperationAction({ISD::UMAX, ISD::UMIN, ISD::SMAX, ISD::SMIN}, VT, in LoongArchTargetLowering()
3807 return DAG.getNode(ISD::SMAX, DL, N->getValueType(0), N->getOperand(1), in performINTRINSIC_WO_CHAINCombine()
3827 return DAG.getNode(ISD::SMAX, DL, N->getValueType(0), N->getOperand(1), in performINTRINSIC_WO_CHAINCombine()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp717 ISD::SMAX, ISD::UMIN, in initActions()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp220 for (auto Opcode : {ISD::ABS, ISD::ABDS, ISD::ABDU, ISD::SMIN, ISD::SMAX, in addTypeForNEON()
271 setOperationAction(ISD::SMAX, VT, Legal); in addMVEVectorTypes()
1040 setTargetDAGCombine({ISD::SMIN, ISD::UMIN, ISD::SMAX, ISD::UMAX, in ARMTargetLowering()
1612 setTargetDAGCombine({ISD::SMIN, ISD::SMAX}); in ARMTargetLowering()
4235 ? ISD::SMIN : ISD::SMAX; in LowerINTRINSIC_WO_CHAIN()
5968 Max = DAG.getNode(ISD::SMAX, DL, VT, Max, in LowerFP_TO_INT_SAT()
17943 (Op0.getOpcode() != ISD::SMIN && Op0.getOpcode() != ISD::SMAX) || in PerformMinMaxToSatCombine()
17951 if (Min.getOpcode() == ISD::SMAX) in PerformMinMaxToSatCombine()
17957 if (Min.getOpcode() != ISD::SMIN || Max.getOpcode() != ISD::SMAX || in PerformMinMaxToSatCombine()
17995 if (Min->getOpcode() != ISD::SMIN || Max->getOpcode() != ISD::SMAX) in PerformMinMaxCombine()
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