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Searched refs:SLLI (Results 1 – 25 of 25) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp230 SDValue SLLI = SDValue( in selectImm() local
231 CurDAG->getMachineNode(RISCV::SLLI, DL, VT, Lo, in selectImm()
234 return SDValue(CurDAG->getMachineNode(AddOpc, DL, VT, Lo, SLLI), 0); in selectImm()
584 unsigned ShOpc = SignExt ? RISCV::SLLIW : RISCV::SLLI; in tryShrinkShlLogicImm()
589 SDNode *SLLI = in tryShrinkShlLogicImm() local
592 ReplaceNode(Node, SLLI); in tryShrinkShlLogicImm()
1196 SDNode *SLLI = CurDAG->getMachineNode( in Select() local
1197 RISCV::SLLI, DL, VT, SDValue(SRLIW, 0), in Select()
1199 ReplaceNode(Node, SLLI); in Select()
1212 SDNode *SLLI = CurDAG->getMachineNode( in Select() local
[all …]
H A DRISCVGISel.td151 def : Pat<(zext (i32 GPR:$src)), (SRLI (i64 (SLLI GPR:$src, 32)), 32)>;
155 (SRLI (XLenVT (SLLI GPR:$src, 16)), 16)>;
159 (SRLI (XLenVT (SLLI GPR:$src, 48)), 48)>;
161 (SRLI (XLenVT (SLLI GPR:$src, 48)), 48)>;
166 (SRAI (XLenVT (SLLI GPR:$src, 16)), 16)>;
170 (SRAI (XLenVT (SLLI GPR:$src, 48)), 48)>;
172 (SRAI (XLenVT (SLLI GPR:$src, 48)), 48)>;
H A DRISCVOptWInstrs.cpp224 case RISCV::SLLI: { in hasAllNBitUsers()
629 case RISCV::SLLI: in isSignExtendedW()
663 case RISCV::SLLI: in getWOp()
738 case RISCV::SLLIW: Opc = RISCV::SLLI; break; in stripWSuffixes()
775 case RISCV::SLLI: in appendWSuffixes()
H A DRISCVInstrInfoM.td120 (MULHU (i64 (SLLI GPR:$rs1, 32)), (i64 (SLLI GPR:$rs2, 32)))>;
H A DRISCVFoldMemOffset.cpp158 case RISCV::SLLI: { in foldOffset()
H A DRISCVRegisterInfo.cpp441 BuildMI(MBB, II, DL, TII->get(RISCV::SLLI), VL) in lowerVSPILL()
524 BuildMI(MBB, II, DL, TII->get(RISCV::SLLI), VL) in lowerVRELOAD()
964 case RISCV::SLLI: in getRegAllocationHints()
H A DRISCVInstrInfo.td785 def SLLI : Shift_ri<0b00000, 0b001, "slli">,
1175 (SLLI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt)>;
1447 def : PatGprUimmLog2XLen<shl, SLLI>;
1469 (SRAI (i32 (SLLI $rs, 31)), 31)>, Requires<[IsRV32]>;
1471 (SRAI (i64 (SLLI $rs, 63)), 63)>, Requires<[IsRV64]>;
1475 (SLLI (i64 (SRLI $rs, (TrailingZeros imm:$mask))),
1478 (SRLI (XLenVT (SLLI $rs, (XLenSubTrailingOnes imm:$mask))),
1623 (SLTIU (XLenVT (SLLI GPR:$rs, (XLenSubTrailingOnes imm:$mask))), 1)>;
1625 (SLTU (XLenVT X0), (XLenVT (SLLI GPR:$rs, (XLenSubTrailingOnes imm:$mask))))>;
2074 def : Pat<(i64 (and GPR:$rs1, 0xffffffff)), (SRLI (i64 (SLLI GPR:$rs1, 32)), 32)>;
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H A DRISCVInstrInfo.cpp1658 case RISCV::SLLI: return RISCV::PseudoCCSLLI; break; in getPredicatedOpcode()
2506 const MachineInstr *ShiftMI = canCombine(MBB, MO, RISCV::SLLI); in canCombineShiftIntoShXAdd()
4170 MI.setDesc(get(RISCV::SLLI)); in simplifyInstruction()
4226 case RISCV::SLLI: in simplifyInstruction()
4497 BuildMI(MBB, II, DL, get(RISCV::SLLI), DestReg) in mulImm()
4521 BuildMI(MBB, II, DL, get(RISCV::SLLI), DestReg) in mulImm()
4532 BuildMI(MBB, II, DL, get(RISCV::SLLI), ScaledRegister) in mulImm()
4543 BuildMI(MBB, II, DL, get(RISCV::SLLI), ScaledRegister) in mulImm()
4564 BuildMI(MBB, II, DL, get(RISCV::SLLI), DestReg) in mulImm()
H A DRISCVExpandPseudoInsts.cpp227 case RISCV::PseudoCCSLLI: NewOpc = RISCV::SLLI; break; in expandCCOp()
H A DRISCVVectorPeephole.cpp246 if (Def->getOpcode() == RISCV::SLLI) { in convertToVLMAX()
H A DRISCVAsmPrinter.cpp765 MCInstBuilder(RISCV::SLLI).addReg(RISCV::X6).addReg(Reg).addImm(8), in EmitHwasanMemaccessSymbols()
H A DRISCVInstrInfoXTHead.td598 (TH_FF0 (i64 (SLLI (i64 (XORI i64:$rs1, -1)), 32)))>;
H A DRISCVInstrInfoZb.td634 (SLLI (XLenVT (PACKH GPR:$rs1, GPR:$rs2)), (XLenVT 16))>;
H A DRISCVInstrInfoC.td983 def : CompressPat<(SLLI GPRNoX0:$rs1, GPRNoX0:$rs1, uimmlog2xlennonzero:$imm),
H A DRISCVFrameLowering.cpp1132 BuildMI(MBB, MBBI, DL, TII->get(RISCV::SLLI), SPReg) in emitPrologue()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMatInt.cpp29 case RISCV::SLLI: in getInstSeqCost()
180 unsigned Opc = Unsigned ? RISCV::SLLI_UW : RISCV::SLLI; in generateInstSeqImpl()
278 TmpSeq.emplace_back(RISCV::SLLI, TrailingZeros); in generateInstSeq()
367 Res[1].getOpcode() == RISCV::SLLI) { in generateInstSeq()
575 case RISCV::SLLI: in getOpndKind()
/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/RISCV/
H A DRISCVInstructions.h142 R_SHAMT_TYPE_INST(SLLI);
278 LWU, LD, SD, SLLI, SRLI, SRAI, ADDIW, SLLIW, SRLIW, SRAIW, ADDW, SUBW, SLLW,
H A DRISCVCInstructions.h233 return SLLI{rd, rd, uint8_t(shamt)}; in DecodeC_SLLI()
H A DEmulateInstructionRISCV.cpp443 {"SLLI", 0xF800707F, 0x1013, DecodeRShamtType<SLLI>},
878 bool operator()(SLLI inst) { in operator ()()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVInstructionSelector.cpp239 case RISCV::SLLI: in hasAllNBitUsers()
519 .buildInstr(RISCV::SLLI, {DstReg}, {RegX}) in selectSHXADD_UWOp()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsScheduleP5600.td441 def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(SLL|SLLI)_[BHWD]$")>;
H A DMipsScheduleGeneric.td1562 def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(SLL|SLLI)_[BHWD]$")>;
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaInstrInfo.td168 def SLLI : RRR_Inst<0x00, 0x01, 0x00, (outs AR:$r), (ins AR:$s, shimm1_31:$sa),
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp3599 emitToStreamer(Out, MCInstBuilder(RISCV::SLLI) in emitPseudoExtend()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchInstrInfo.td592 // Check if (mul r, imm) can be optimized to (SLLI (ALSL r, r, i0), i1),