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Searched refs:SIGN_EXTEND (Results 1 – 25 of 62) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyTargetTransformInfo.cpp106 (ISD == ISD::ZERO_EXTEND || ISD == ISD::SIGN_EXTEND)) { in getCastInstrCost()
124 {ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i32, 1}, in getCastInstrCost()
126 {ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 1}, in getCastInstrCost()
128 {ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 1}, in getCastInstrCost()
130 {ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i16, 2}, in getCastInstrCost()
132 {ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 2}, in getCastInstrCost()
H A DWebAssemblyISelLowering.cpp201 setTargetDAGCombine({ISD::SIGN_EXTEND, ISD::ZERO_EXTEND}); in WebAssemblyTargetLowering()
2123 bool IsSigned = ExtendLHS->getOpcode() == ISD::SIGN_EXTEND; in performLowerPartialReduction()
2932 N->getOpcode() == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND; in performVectorExtendToFPCombine()
2940 assert(N->getOpcode() == ISD::SIGN_EXTEND || in performVectorExtendCombine()
2973 bool IsSext = N->getOpcode() == ISD::SIGN_EXTEND; in performVectorExtendCombine()
3427 if (LHS.getOpcode() != ISD::SIGN_EXTEND && in performMulCombine()
3463 bool IsSigned = LHS->getOpcode() == ISD::SIGN_EXTEND; in performMulCombine()
3514 case ISD::SIGN_EXTEND: in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp2301 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, { 1, 1, 1, 1 } }, in getCastInstrCost()
2305 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, { 1, 1, 1, 1 } }, in getCastInstrCost()
2306 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v2i1, { 1, 1, 1, 1 } }, in getCastInstrCost()
2307 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, { 1, 1, 1, 1 } }, in getCastInstrCost()
2308 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v2i1, { 1, 1, 1, 1 } }, in getCastInstrCost()
2309 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, { 1, 1, 1, 1 } }, in getCastInstrCost()
2310 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v4i1, { 1, 1, 1, 1 } }, in getCastInstrCost()
2311 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, { 1, 1, 1, 1 } }, in getCastInstrCost()
2312 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v4i1, { 1, 1, 1, 1 } }, in getCastInstrCost()
2313 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, { 1, 1, 1, 1 } }, in getCastInstrCost()
[all …]
H A DX86ISelLowering.cpp1024 setOperationAction(ISD::SIGN_EXTEND, VT, Expand); in X86TargetLowering()
1287 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom); in X86TargetLowering()
1530 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom); in X86TargetLowering()
1531 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom); in X86TargetLowering()
1544 setOperationAction(ISD::SIGN_EXTEND, VT, Custom); in X86TargetLowering()
1763 setOperationAction(ISD::SIGN_EXTEND, VT, Custom); in X86TargetLowering()
1898 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom); in X86TargetLowering()
1899 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom); in X86TargetLowering()
1900 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom); in X86TargetLowering()
1904 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom); in X86TargetLowering()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp543 {ISD::SIGN_EXTEND, MVT::i32, MVT::i16, 0}, in getCastInstrCost()
545 {ISD::SIGN_EXTEND, MVT::i32, MVT::i8, 0}, in getCastInstrCost()
547 {ISD::SIGN_EXTEND, MVT::i16, MVT::i8, 0}, in getCastInstrCost()
549 {ISD::SIGN_EXTEND, MVT::i64, MVT::i32, 1}, in getCastInstrCost()
551 {ISD::SIGN_EXTEND, MVT::i64, MVT::i16, 1}, in getCastInstrCost()
553 {ISD::SIGN_EXTEND, MVT::i64, MVT::i8, 1}, in getCastInstrCost()
561 {ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0}, in getCastInstrCost()
563 {ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 0}, in getCastInstrCost()
565 {ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 0}, in getCastInstrCost()
570 {ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1}, in getCastInstrCost()
[all …]
H A DARMISelLowering.cpp170 DAG.getNode(Arg.Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, DL, in handleCMSEValue()
496 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom); in addMVEVectorTypes()
497 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom); in addMVEVectorTypes()
498 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom); in addMVEVectorTypes()
1033 ISD::SIGN_EXTEND_INREG, ISD::STORE, ISD::SIGN_EXTEND, ISD::ZERO_EXTEND, in ARMTargetLowering()
2624 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
6077 CastOpc = ISD::SIGN_EXTEND; in LowerVectorINT_TO_FP()
9453 N->getOpcode() == ISD::SIGN_EXTEND ? ARMISD::MVESEXT : ARMISD::MVEZEXT; in LowerVectorExtend()
9522 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N)) in isSignExtended()
9607 if (N->getOpcode() == ISD::SIGN_EXTEND || in SkipExtensionForVMULL()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGAddressAnalysis.cpp280 if (Index->getOpcode() == ISD::SIGN_EXTEND) { in matchLSNode()
291 if (Index->getOpcode() == ISD::SIGN_EXTEND) { in matchLSNode()
H A DDAGCombiner.cpp1512 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in PromoteOperand()
1965 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); in visit()
2108 case ISD::SIGN_EXTEND: in combine()
2852 if (N0.getOpcode() == ISD::SIGN_EXTEND && N0.hasOneUse() && in visitADDLike()
3351 if (N0.getOpcode() == ISD::SIGN_EXTEND && in visitADDLikeCommutative()
4329 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, VT, N1.getOperand(0)); in visitSUB()
5447 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0); in visitMULHS()
5448 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1); in visitMULHS()
5589 return DAG.getNode(ISD::SIGN_EXTEND, DL, VT, AvgS); in visitAVG()
5758 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0); in visitSMUL_LOHI()
[all …]
H A DFunctionLoweringInfo.cpp81 ExtendKind = ISD::SIGN_EXTEND; in getPreferredExtendForValue()
H A DLegalizeVectorTypes.cpp127 case ISD::SIGN_EXTEND: in ScalarizeVectorResult()
522 return DAG.getNode(ISD::SIGN_EXTEND, DL, EltVT, Op); in ScalarizeVecRes_VecInregOp()
755 case ISD::SIGN_EXTEND: in ScalarizeVectorOperand()
1282 case ISD::SIGN_EXTEND: in SplitVectorResult()
3475 case ISD::SIGN_EXTEND: in SplitVectorOperand()
4873 case ISD::SIGN_EXTEND: in WidenVectorResult()
5460 if (Opcode == ISD::SIGN_EXTEND) in WidenVecRes_Convert()
5630 Val = DAG.getNode(ISD::SIGN_EXTEND, DL, WidenSVT, Val); in WidenVecRes_EXTEND_VECTOR_INREG()
6382 else if (N.getOpcode() == ISD::SIGN_EXTEND) in isSETCCorConvertedSETCC()
6424 Mask = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(Mask), ExtVT, Mask); in convertMask()
[all …]
H A DLegalizeDAG.cpp2932 DAG.getNode(IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, in PromoteLegalINT_TO_FP()
2941 DAG.getNode(IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, in PromoteLegalINT_TO_FP()
3217 case ISD::SIGN_EXTEND: in ExpandNode()
5044 SDValue Op = DAG.getNode(Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl, in ConvertNodeToLibcall()
5465 ExtOp = ISD::SIGN_EXTEND; in PromoteNode()
5474 ExtOp = ISD::SIGN_EXTEND; in PromoteNode()
5493 : ISD::SIGN_EXTEND; in PromoteNode()
5564 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in PromoteNode()
5600 ExtOp = ISD::SIGN_EXTEND; in PromoteNode()
5630 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in PromoteNode()
H A DLegalizeIntegerTypes.cpp173 case ISD::SIGN_EXTEND: in PromoteIntegerResult()
392 case ISD::SIGN_EXTEND: in PromoteIntRes_Atomic0()
455 case ISD::SIGN_EXTEND: in PromoteIntRes_AtomicCmpSwap()
681 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in PromoteIntRes_Constant()
945 if (N->getOpcode() == ISD::SIGN_EXTEND) in PromoteIntRes_INT_EXTEND()
1990 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break; in PromoteIntegerOperand()
2715 return ISD::SIGN_EXTEND; in getExtendForIntVecReduction()
2730 case ISD::SIGN_EXTEND: in PromoteIntOpVectorReduction()
2999 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break; in ExpandIntegerResult()
4856 N->getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in ExpandIntRes_ShiftThroughStack()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h826 SIGN_EXTEND, enumerator
1758 Opcode == ISD::SIGN_EXTEND; in isExtOpcode()
H A DSelectionDAG.h991 case ISD::SIGN_EXTEND:
993 return ISD::SIGN_EXTEND;
1007 case ISD::SIGN_EXTEND:
1036 case ISD::SIGN_EXTEND:
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp3172 {ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3}, in getCastInstrCost()
3174 {ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2}, in getCastInstrCost()
3176 {ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3}, in getCastInstrCost()
3178 {ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2}, in getCastInstrCost()
3180 {ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7}, in getCastInstrCost()
3182 {ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 6}, in getCastInstrCost()
3184 {ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2}, in getCastInstrCost()
3186 {ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6}, in getCastInstrCost()
3549 {ISD::SIGN_EXTEND, MVT::nxv16i16, MVT::nxv16i8, 2}, in getCastInstrCost()
3550 {ISD::SIGN_EXTEND, MVT::nxv16i32, MVT::nxv16i8, 6}, in getCastInstrCost()
[all …]
H A DAArch64ISelLowering.cpp1142 setTargetDAGCombine({ISD::ANY_EXTEND, ISD::ZERO_EXTEND, ISD::SIGN_EXTEND, in AArch64TargetLowering()
2328 setOperationAction(ISD::SIGN_EXTEND, VT, Default); in addTypeForFixedLengthSVE()
4022 unsigned ExtendOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in getAArch64XALUOOp()
4032 SDValue SExtMul = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Value); in getAArch64XALUOOp()
4903 unsigned CastOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerVectorINT_TO_FP()
5214 return N.getOpcode() == ISD::SIGN_EXTEND || in isSignExtended()
5702 {SVL, DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, VarAddend)}); in LowerSMELdrStr()
5766 Mask = DAG.getNode(ISD::SIGN_EXTEND, DL, Op1VT, Mask); in LowerVectorMatch()
5775 Match = DAG.getNode(ISD::SIGN_EXTEND, DL, OpContainerVT, Match); in LowerVectorMatch()
6366 SDValue Mask = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, CttzOp); in LowerINTRINSIC_WO_CHAIN()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp241 setOperationAction(ISD::SIGN_EXTEND, T, Custom); in initializeHVXLowering()
284 setOperationAction(ISD::SIGN_EXTEND, T, Custom); in initializeHVXLowering()
433 setOperationAction(ISD::SIGN_EXTEND, VecTy, Custom); in initializeHVXLowering()
1259 ValV = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, ValV); in insertHvxElementPred()
1601 unsigned ExtOpc = Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in resizeToWidth()
2939 case ISD::SIGN_EXTEND: in CreateTLWrapper()
3227 case ISD::SIGN_EXTEND: in LowerHvxOperation()
3249 case ISD::SIGN_EXTEND: return LowerHvxSignExt(Op, DAG); in LowerHvxOperation()
3305 case ISD::SIGN_EXTEND: in ExpandHvxResizeIntoSteps()
3405 case ISD::SIGN_EXTEND: in LowerHvxOperationWrapper()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.h268 return ISD::SIGN_EXTEND; in getExtendForAtomicOps()
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp97 setOperationAction(ISD::SIGN_EXTEND, MVT::i16, Custom); in MSP430TargetLowering()
230 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG); in LowerOperation()
718 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp659 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg); in LowerCall()
1102 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), ValToCopy); in LowerReturn()
1107 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), ValToCopy); in LowerReturn()
1603 PromoteMULO(ISD::SIGN_EXTEND); in lowerOverflowArithmetic()
2120 isM68kCCUnsigned(M68kCC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND; in EmitCmp()
3544 Carry.getOpcode() == ISD::SIGN_EXTEND || in combineCarryThroughADD()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp2940 case ISD::SIGN_EXTEND: in Select()
2958 N->getOpcode() == ISD::SIGN_EXTEND) && in tryEXTEND()
2972 N->getOpcode() == ISD::SIGN_EXTEND ? in tryEXTEND()
2981 NumSextSetcc += N->getOpcode() == ISD::SIGN_EXTEND ? 1 : 0; in tryEXTEND()
2982 NumZextSetcc += N->getOpcode() == ISD::SIGN_EXTEND ? 0 : 1; in tryEXTEND()
3154 Input.getOperand(0).getOpcode() == ISD::SIGN_EXTEND)) in signExtendInputIfNeeded()
3989 if (CompareUse->getOpcode() != ISD::SIGN_EXTEND && in allUsesExtend()
4067 case ISD::SIGN_EXTEND: in tryIntCompareInGPR()
4698 (TrueResVal == 1 && FalseRes.getOpcode() != ISD::SIGN_EXTEND) || in mayUseP9Setb()
6608 N->getOpcode() != ISD::SIGN_EXTEND && in foldBoolExts()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.h322 return ISD::SIGN_EXTEND; in getExtendForAtomicOps()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp572 AddPromotedToType(ISD::SIGN_EXTEND, MVT::i16, MVT::i32); in SITargetLowering()
577 setOperationAction({ISD::SIGN_EXTEND, ISD::SDIV, ISD::UDIV, ISD::SREM, in SITargetLowering()
750 setOperationAction({ISD::ANY_EXTEND, ISD::ZERO_EXTEND, ISD::SIGN_EXTEND}, in SITargetLowering()
754 setOperationAction({ISD::ANY_EXTEND, ISD::ZERO_EXTEND, ISD::SIGN_EXTEND}, in SITargetLowering()
757 setOperationAction({ISD::ANY_EXTEND, ISD::ZERO_EXTEND, ISD::SIGN_EXTEND}, in SITargetLowering()
3328 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg); in LowerReturn()
3939 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg); in LowerCall()
6374 ICmpInst::isSigned(IcInput) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in lowerICMPIntrinsic()
7195 return ISD::SIGN_EXTEND; in getExtOpcodeForPromotedOp()
7213 return ISD::isSignedIntSetCC(CC) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in getExtOpcodeForPromotedOp()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp664 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg); in LowerCCCCallTo()
1337 case ISD::SIGN_EXTEND: { in isConditionalZeroOrAllOnes()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h244 return ISD::SIGN_EXTEND; in getExtendForAtomicOps()

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