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Searched refs:SIGN_EXTEND (Results 1 – 25 of 61) sorted by relevance

123

/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp2184 { ISD::SIGN_EXTEND, MVT::v32i16, MVT::v32i8, { 1, 1, 1, 1 } }, in getCastInstrCost()
2188 { ISD::SIGN_EXTEND, MVT::v2i8, MVT::v2i1, { 1, 1, 1, 1 } }, in getCastInstrCost()
2189 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v2i1, { 1, 1, 1, 1 } }, in getCastInstrCost()
2190 { ISD::SIGN_EXTEND, MVT::v2i16, MVT::v2i1, { 1, 1, 1, 1 } }, in getCastInstrCost()
2191 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v2i1, { 1, 1, 1, 1 } }, in getCastInstrCost()
2192 { ISD::SIGN_EXTEND, MVT::v4i8, MVT::v4i1, { 1, 1, 1, 1 } }, in getCastInstrCost()
2193 { ISD::SIGN_EXTEND, MVT::v16i8, MVT::v4i1, { 1, 1, 1, 1 } }, in getCastInstrCost()
2194 { ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i1, { 1, 1, 1, 1 } }, in getCastInstrCost()
2195 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v4i1, { 1, 1, 1, 1 } }, in getCastInstrCost()
2196 { ISD::SIGN_EXTEND, MVT::v8i8, MVT::v8i1, { 1, 1, 1, 1 } }, in getCastInstrCost()
[all …]
H A DX86ISelLowering.cpp1011 setOperationAction(ISD::SIGN_EXTEND, VT, Expand); in X86TargetLowering()
1266 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom); in X86TargetLowering()
1506 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom); in X86TargetLowering()
1507 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom); in X86TargetLowering()
1520 setOperationAction(ISD::SIGN_EXTEND, VT, Custom); in X86TargetLowering()
1734 setOperationAction(ISD::SIGN_EXTEND, VT, Custom); in X86TargetLowering()
1866 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom); in X86TargetLowering()
1867 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom); in X86TargetLowering()
1868 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom); in X86TargetLowering()
1872 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom); in X86TargetLowering()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp523 {ISD::SIGN_EXTEND, MVT::i32, MVT::i16, 0}, in getCastInstrCost()
525 {ISD::SIGN_EXTEND, MVT::i32, MVT::i8, 0}, in getCastInstrCost()
527 {ISD::SIGN_EXTEND, MVT::i16, MVT::i8, 0}, in getCastInstrCost()
529 {ISD::SIGN_EXTEND, MVT::i64, MVT::i32, 1}, in getCastInstrCost()
531 {ISD::SIGN_EXTEND, MVT::i64, MVT::i16, 1}, in getCastInstrCost()
533 {ISD::SIGN_EXTEND, MVT::i64, MVT::i8, 1}, in getCastInstrCost()
541 {ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0}, in getCastInstrCost()
543 {ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i8, 0}, in getCastInstrCost()
545 {ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 0}, in getCastInstrCost()
550 {ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1}, in getCastInstrCost()
[all …]
H A DARMISelLowering.cpp165 DAG.getNode(Arg.Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, DL, in handleCMSEValue()
486 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom); in addMVEVectorTypes()
487 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom); in addMVEVectorTypes()
488 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom); in addMVEVectorTypes()
1035 ISD::SIGN_EXTEND_INREG, ISD::STORE, ISD::SIGN_EXTEND, ISD::ZERO_EXTEND, in ARMTargetLowering()
2515 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
6004 CastOpc = ISD::SIGN_EXTEND; in LowerVectorINT_TO_FP()
9401 N->getOpcode() == ISD::SIGN_EXTEND ? ARMISD::MVESEXT : ARMISD::MVEZEXT; in LowerVectorExtend()
9470 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N)) in isSignExtended()
9555 if (N->getOpcode() == ISD::SIGN_EXTEND || in SkipExtensionForVMULL()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h802 SIGN_EXTEND, enumerator
1647 Opcode == ISD::SIGN_EXTEND; in isExtOpcode()
H A DSelectionDAG.h928 case ISD::SIGN_EXTEND:
930 return ISD::SIGN_EXTEND;
944 case ISD::SIGN_EXTEND:
973 case ISD::SIGN_EXTEND:
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGAddressAnalysis.cpp279 if (Index->getOpcode() == ISD::SIGN_EXTEND) { in matchLSNode()
291 if (Index->getOpcode() == ISD::SIGN_EXTEND) { in matchLSNode()
H A DDAGCombiner.cpp1455 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in PromoteOperand()
1907 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); in visit()
2039 case ISD::SIGN_EXTEND: in combine()
2690 if (N0.getOpcode() == ISD::SIGN_EXTEND && N0.hasOneUse() && in visitADDLike()
3191 if (N0.getOpcode() == ISD::SIGN_EXTEND && in visitADDLikeCommutative()
4025 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, VT, N1.getOperand(0)); in visitSUB()
5103 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0); in visitMULHS()
5104 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1); in visitMULHS()
5245 return DAG.getNode(ISD::SIGN_EXTEND, DL, VT, AvgS); in visitAVG()
5383 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0); in visitSMUL_LOHI()
[all …]
H A DLegalizeIntegerTypes.cpp155 case ISD::SIGN_EXTEND: in PromoteIntegerResult()
377 case ISD::SIGN_EXTEND: in PromoteIntRes_Atomic0()
438 case ISD::SIGN_EXTEND: in PromoteIntRes_AtomicCmpSwap()
641 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in PromoteIntRes_Constant()
923 if (N->getOpcode() == ISD::SIGN_EXTEND) in PromoteIntRes_INT_EXTEND()
1942 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break; in PromoteIntegerOperand()
2579 return ISD::SIGN_EXTEND; in getExtendForIntVecReduction()
2594 case ISD::SIGN_EXTEND: in PromoteIntOpVectorReduction()
2816 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break; in ExpandIntegerResult()
4624 N->getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in ExpandIntRes_ShiftThroughStack()
[all …]
H A DFunctionLoweringInfo.cpp81 ExtendKind = ISD::SIGN_EXTEND; in getPreferredExtendForValue()
H A DLegalizeDAG.cpp2905 DAG.getNode(IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, in PromoteLegalINT_TO_FP()
2914 DAG.getNode(IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, in PromoteLegalINT_TO_FP()
3187 case ISD::SIGN_EXTEND: in ExpandNode()
4835 SDValue Op = DAG.getNode(Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl, in ConvertNodeToLibcall()
5254 ExtOp = ISD::SIGN_EXTEND; in PromoteNode()
5263 ExtOp = ISD::SIGN_EXTEND; in PromoteNode()
5282 : ISD::SIGN_EXTEND; in PromoteNode()
5354 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in PromoteNode()
5390 ExtOp = ISD::SIGN_EXTEND; in PromoteNode()
5420 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in PromoteNode()
H A DLegalizeVectorTypes.cpp123 case ISD::SIGN_EXTEND: in ScalarizeVectorResult()
516 return DAG.getNode(ISD::SIGN_EXTEND, DL, EltVT, Op); in ScalarizeVecRes_VecInregOp()
751 case ISD::SIGN_EXTEND: in ScalarizeVectorOperand()
1228 case ISD::SIGN_EXTEND: in SplitVectorResult()
3200 case ISD::SIGN_EXTEND: in SplitVectorOperand()
4504 case ISD::SIGN_EXTEND: in WidenVectorResult()
5069 if (Opcode == ISD::SIGN_EXTEND) in WidenVecRes_Convert()
5243 Val = DAG.getNode(ISD::SIGN_EXTEND, DL, WidenSVT, Val); in WidenVecRes_EXTEND_VECTOR_INREG()
5938 else if (N.getOpcode() == ISD::SIGN_EXTEND) in isSETCCorConvertedSETCC()
5980 Mask = DAG.getNode(ISD::SIGN_EXTEND, SDLo in convertMask()
[all...]
H A DSelectionDAG.cpp318 if (N->getOpcode() == ISD::SIGN_EXTEND) { in isVectorShrinkable()
570 return ISD::SIGN_EXTEND; in getExtForLoadExtType()
1462 getNode(ISD::SIGN_EXTEND, DL, VT, Op) : in getSExtOrTrunc()
2782 case ISD::SIGN_EXTEND: in isSplatValue()
3829 case ISD::SIGN_EXTEND: { in computeKnownBits()
4593 case ISD::SIGN_EXTEND: in ComputeNumSignBits()
5029 if (TLI->getExtendForAtomicOps() == ISD::SIGN_EXTEND) in ComputeNumSignBits()
5277 case ISD::SIGN_EXTEND: in canCreateUndefOrPoison()
5652 case ISD::SIGN_EXTEND: in isKnownNeverZero()
5929 case ISD::SIGN_EXTEND: in getNode()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp2563 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, in getCastInstrCost()
2565 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, in getCastInstrCost()
2567 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost()
2569 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 }, in getCastInstrCost()
2571 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i8, 7 }, in getCastInstrCost()
2573 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 6 }, in getCastInstrCost()
2575 { ISD::SIGN_EXTEND, MVT::v16i16, MVT::v16i8, 2 }, in getCastInstrCost()
2577 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 }, in getCastInstrCost()
2784 { ISD::SIGN_EXTEND, MVT::nxv16i16, MVT::nxv16i8, 2}, in getCastInstrCost()
2785 { ISD::SIGN_EXTEND, MVT::nxv16i32, MVT::nxv16i8, 6}, in getCastInstrCost()
[all …]
H A DAArch64ISelLowering.cpp1100 setTargetDAGCombine({ISD::ANY_EXTEND, ISD::ZERO_EXTEND, ISD::SIGN_EXTEND, in AArch64TargetLowering()
2091 setOperationAction(ISD::SIGN_EXTEND, VT, Default); in addTypeForFixedLengthSVE()
4009 unsigned ExtendOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in getAArch64XALUOOp()
4019 SDValue SExtMul = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Value); in getAArch64XALUOOp()
4658 unsigned CastOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerVectorINT_TO_FP()
4707 unsigned CastOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in LowerVectorINT_TO_FP()
5056 return N.getOpcode() == ISD::SIGN_EXTEND || in isSignExtended()
5530 {SVL, DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, VarAddend)}); in LowerSMELdrStr()
6046 SDValue MaskAsInt = DAG.getNode(ISD::SIGN_EXTEND, dl, ContainerVT, Mask); in LowerINTRINSIC_WO_CHAIN()
6074 SDValue Mask = DAG.getNode(ISD::SIGN_EXTEND, dl, NewVT, CttzOp); in LowerINTRINSIC_WO_CHAIN()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.h220 return ISD::SIGN_EXTEND; in getExtendForAtomicOps()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp237 setOperationAction(ISD::SIGN_EXTEND, T, Custom); in initializeHVXLowering()
280 setOperationAction(ISD::SIGN_EXTEND, T, Custom); in initializeHVXLowering()
423 setOperationAction(ISD::SIGN_EXTEND, VecTy, Custom); in initializeHVXLowering()
1248 ValV = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, ValV); in insertHvxElementPred()
1585 unsigned ExtOpc = Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in resizeToWidth()
2902 case ISD::SIGN_EXTEND: in CreateTLWrapper()
3190 case ISD::SIGN_EXTEND: in LowerHvxOperation()
3212 case ISD::SIGN_EXTEND: return LowerHvxSignExt(Op, DAG); in LowerHvxOperation()
3268 case ISD::SIGN_EXTEND: in ExpandHvxResizeIntoSteps()
3368 case ISD::SIGN_EXTEND in LowerHvxOperationWrapper()
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp657 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg); in LowerCall()
1100 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), ValToCopy); in LowerReturn()
1105 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), ValToCopy); in LowerReturn()
1601 PromoteMULO(ISD::SIGN_EXTEND); in lowerOverflowArithmetic()
2118 isM68kCCUnsigned(M68kCC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND; in EmitCmp()
3544 Carry.getOpcode() == ISD::SIGN_EXTEND || in combineCarryThroughADD()
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp98 setOperationAction(ISD::SIGN_EXTEND, MVT::i16, Custom); in MSP430TargetLowering()
351 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG); in LowerOperation()
838 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp183 setTargetDAGCombine({ISD::SIGN_EXTEND, ISD::ZERO_EXTEND}); in WebAssemblyTargetLowering()
2522 N->getOpcode() == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND; in performVectorExtendToFPCombine()
2530 assert(N->getOpcode() == ISD::SIGN_EXTEND || in performVectorExtendCombine()
2563 bool IsSext = N->getOpcode() == ISD::SIGN_EXTEND; in performVectorExtendCombine()
2891 case ISD::SIGN_EXTEND: in PerformDAGCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp2940 case ISD::SIGN_EXTEND: in Select()
2958 N->getOpcode() == ISD::SIGN_EXTEND) && in tryEXTEND()
2972 N->getOpcode() == ISD::SIGN_EXTEND ? in tryEXTEND()
2982 NumSextSetcc += N->getOpcode() == ISD::SIGN_EXTEND ? 1 : 0; in tryEXTEND()
2983 NumZextSetcc += N->getOpcode() == ISD::SIGN_EXTEND ? 0 : 1; in tryEXTEND()
3155 Input.getOperand(0).getOpcode() == ISD::SIGN_EXTEND)) in signExtendInputIfNeeded()
3990 if (CompareUse->getOpcode() != ISD::SIGN_EXTEND && in allUsesExtend()
4068 case ISD::SIGN_EXTEND: in tryIntCompareInGPR()
4699 (TrueResVal == 1 && FalseRes.getOpcode() != ISD::SIGN_EXTEND) || in mayUseP9Setb()
6595 N->getOpcode() != ISD::SIGN_EXTEND && in foldBoolExts()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.h320 return ISD::SIGN_EXTEND; in getExtendForAtomicOps()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp835 setOperationAction({ISD::ANY_EXTEND, ISD::SIGN_EXTEND, ISD::ZERO_EXTEND}, in RISCVTargetLowering()
1256 {ISD::ANY_EXTEND, ISD::SIGN_EXTEND, ISD::ZERO_EXTEND}, VT, Custom); in RISCVTargetLowering()
4324 isa<ConstantSDNode>(Scalar) ? ISD::SIGN_EXTEND : ISD::ANY_EXTEND; in lowerScalarSplat()
4391 isa<ConstantSDNode>(Scalar) ? ISD::SIGN_EXTEND : ISD::ANY_EXTEND; in lowerScalarInsert()
5693 SDValue LHS = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Op.getOperand(0)); in lowerSADDSAT_SSUBSAT()
5694 SDValue RHS = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Op.getOperand(1)); in lowerSADDSAT_SSUBSAT()
5715 SDValue LHS = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Op.getOperand(0)); in lowerUADDSAT_USUBSAT()
5716 SDValue RHS = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Op.getOperand(1)); in lowerUADDSAT_USUBSAT()
5730 SDValue LHS = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Op.getOperand(0)); in lowerSADDO_SSUBO()
5731 SDValue RHS = DAG.getNode(ISD::SIGN_EXTEND, D in lowerSADDO_SSUBO()
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp556 AddPromotedToType(ISD::SIGN_EXTEND, MVT::i16, MVT::i32); in SITargetLowering()
561 setOperationAction({ISD::SIGN_EXTEND, ISD::SDIV, ISD::UDIV, ISD::SREM, in SITargetLowering()
734 setOperationAction({ISD::ANY_EXTEND, ISD::ZERO_EXTEND, ISD::SIGN_EXTEND}, in SITargetLowering()
738 setOperationAction({ISD::ANY_EXTEND, ISD::ZERO_EXTEND, ISD::SIGN_EXTEND}, in SITargetLowering()
741 setOperationAction({ISD::ANY_EXTEND, ISD::ZERO_EXTEND, ISD::SIGN_EXTEND}, in SITargetLowering()
3208 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg); in LowerReturn()
3770 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg); in LowerCall()
6030 ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in lowerICMPIntrinsic()
10160 return DAG.getNode(ISD::SIGN_EXTEND, SL, VT, Op); in getLoadExtOrTrunc()
11631 (RHS.getOpcode() == ISD::SIGN_EXTEND || LHS.getOpcode() == ISD::SIGN_EXTEND)) { in performAndCombine()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp673 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg); in LowerCCCCallTo()
1383 case ISD::SIGN_EXTEND: { in isConditionalZeroOrAllOnes()

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