1100   setTargetDAGCombine({ISD::ANY_EXTEND, ISD::ZERO_EXTEND, ISD::SIGN_EXTEND,  in AArch64TargetLowering()
2091   setOperationAction(ISD::SIGN_EXTEND, VT, Default);  in addTypeForFixedLengthSVE()
4009       unsigned ExtendOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;  in getAArch64XALUOOp()
4019         SDValue SExtMul = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Value);  in getAArch64XALUOOp()
4658       unsigned CastOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;  in LowerVectorINT_TO_FP()
4707     unsigned CastOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;  in LowerVectorINT_TO_FP()
5056   return N.getOpcode() == ISD::SIGN_EXTEND ||  in isSignExtended()
5530         {SVL, DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, VarAddend)});  in LowerSMELdrStr()
6046     SDValue MaskAsInt = DAG.getNode(ISD::SIGN_EXTEND, dl, ContainerVT, Mask);  in LowerINTRINSIC_WO_CHAIN()
6074       SDValue Mask = DAG.getNode(ISD::SIGN_EXTEND, dl, NewVT, CttzOp);  in LowerINTRINSIC_WO_CHAIN()
6248     unsigned ExtOpcode = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;  in LowerMGATHER()
6250     Mask = DAG.getNode(ISD::SIGN_EXTEND, DL, PromotedVT, Mask);  in LowerMGATHER()
6338     unsigned ExtOpcode = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;  in LowerMSCATTER()
6340     Mask = DAG.getNode(ISD::SIGN_EXTEND, DL, PromotedVT, Mask);  in LowerMSCATTER()
6572     ExtType = ISD::SIGN_EXTEND;  in LowerLOAD()
6672     Exp = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Exp);  in LowerFLDEXP()
6973   case ISD::SIGN_EXTEND:  in LowerOperation()
8501       Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);  in LowerCall()
9794   if (Val.getOpcode() == ISD::SIGN_EXTEND)  in lookThroughSignExtension()
15214         ScalarOpcode == ISD::XOR ? ISD::ANY_EXTEND : ISD::SIGN_EXTEND;  in getVectorBitwiseReduce()
17672   } else if (Opcode0 == ISD::SIGN_EXTEND && Opcode1 == ISD::SIGN_EXTEND) {  in performVecReduceAddCombineWithUADDLP()
17747   if (ExtOpcode != ISD::ZERO_EXTEND && ExtOpcode != ISD::SIGN_EXTEND)  in performVecReduceAddCombine()
17839          Op0.getOpcode() != ISD::SIGN_EXTEND))  in performUADDVAddCombine()
18049   case ISD::SIGN_EXTEND:  in calculatePreExtendType()
18095   bool IsSExt = ExtendOpcode == ISD::SIGN_EXTEND ||  in performBuildShuffleExtendCombine()
18104       ExtendOpcode != ISD::SIGN_EXTEND && ExtendOpcode != ISD::ZERO_EXTEND)  in performBuildShuffleExtendCombine()
18118     bool OpcIsSExt = Opc == ISD::SIGN_EXTEND || Opc == ISD::SIGN_EXTEND_INREG ||  in performBuildShuffleExtendCombine()
18144   return DAG.getNode(IsSExt ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, DL, VT, NBV);  in performBuildShuffleExtendCombine()
18210        N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND) ||  in performVectorExtCombine()
18212        N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND) ||  in performVectorExtCombine()
18237                                                   : (unsigned)ISD::SIGN_EXTEND,  in performVectorExtCombine()
20052        LHS.getOpcode() != ISD::SIGN_EXTEND) ||  in performAddSubLongCombine()
20610   case ISD::SIGN_EXTEND:  in areLoadedOffsetButOtherwiseSame()
21556   assert(N->getOpcode() == ISD::SIGN_EXTEND &&  in performSignExtendSetCCCombine()
21570       isSignedIntSetCC(Code) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;  in performSignExtendSetCCCombine()
21607       N->getOpcode() == ISD::SIGN_EXTEND &&  in performExtendCombine()
22411   if (N->getOperand(0).getOpcode() == ISD::SIGN_EXTEND &&  in performSunpkloCombine()
22418     return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), N->getValueType(0), Unpk);  in performSunpkloCombine()
22566     if (ExtOpCode != ISD::ZERO_EXTEND && ExtOpCode != ISD::SIGN_EXTEND &&  in foldTruncStoreOfExt()
23843   SDNode *Op0SExt = DAG.getNodeIfExists(ISD::SIGN_EXTEND, DAG.getVTList(UseMVT),  in tryToWidenSetCCOperands()
23849     Op1ExtV = DAG.getNode(ISD::SIGN_EXTEND, DL, UseMVT, Op->getOperand(1));  in tryToWidenSetCCOperands()
23937       LHS = DAG.getNode(IsNull ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND, DL, ToVT,  in performSETCCCombine()
23985       LHS->getOpcode() != ISD::SIGN_EXTEND)  in performSetCCPunpkCombine()
24028       LHS->getOpcode() == ISD::SIGN_EXTEND &&  in performSetccMergeZeroCombine()
25323   case ISD::SIGN_EXTEND:  in PerformDAGCombine()
27418   unsigned ExtendOpcode = Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;  in LowerFixedLengthVectorIntDivideToSVE()
27461   bool Signed = Op.getOpcode() == ISD::SIGN_EXTEND;  in LowerFixedLengthVectorIntExtendToSVE()
27911     Val = DAG.getNode(IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, DL,  in LowerFixedLengthIntToFPToSVE()