Searched refs:SHL_PRED (Results 1 – 4 of 4) sorted by relevance
130 SHL_PRED, enumerator
4497 if (N0.getOpcode() != AArch64ISD::SHL_PRED || in trySelectXAR()4500 if (N0.getOpcode() != AArch64ISD::SHL_PRED || in trySelectXAR()
2571 MAKE_CASE(AArch64ISD::SHL_PRED) in getTargetNodeName()13707 SecondOpc == AArch64ISD::SHL_PRED || in tryLowerToSLI()13714 FirstOpc == AArch64ISD::SHL_PRED || in tryLowerToSLI()13724 bool ShiftHasPredOp = Shift.getOpcode() == AArch64ISD::SHL_PRED || in tryLowerToSLI()14900 return LowerToPredicatedOp(Op, DAG, AArch64ISD::SHL_PRED); in LowerVectorSRA_SRL_SHL()21354 return DAG.getNode(AArch64ISD::SHL_PRED, SDLoc(N), N->getValueType(0), in performIntrinsicCombine()
194 def AArch64lsl_p : SDNode<"AArch64ISD::SHL_PRED", SDT_AArch64Arith>;