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Searched refs:SHADD (Results 1 – 6 of 6) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedCyclone.td418 // SHADD,SHSUB,SRHADD,UHADD,UHSUB,URHADD
H A DAArch64SchedAmpere1.td1030 (instregex "^ABSv", "^(ADD|SUB)v", "^SADDLv", "^SADDW", "SHADD",
H A DAArch64SchedAmpere1B.td1037 (instregex "^ABSv", "^(ADD|SUB)v", "^SADDLv", "^SADDW", "SHADD",
H A DAArch64InstrInfo.td6020 defm SHADD : SIMDThreeSameVectorBHS<0,0b00000,"shadd", avgfloors>;
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleA57.td318 "(t2)?SHADD(16|8)", "(t2)?SHSUB(16|8)",
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp15085 SDValue SHADD = DAG.getNode(RISCVISD::SHL_ADD, DL, VT, NL, in transformAddShlImm() local
15087 return DAG.getNode(ISD::SHL, DL, VT, SHADD, DAG.getConstant(Bits, DL, VT)); in transformAddShlImm()
15123 SDValue SHADD = DAG.getNode(RISCVISD::SHL_ADD, DL, VT, SHLVal->getOperand(0), in combineShlAddIAddImpl() local
15125 return DAG.getNode(ISD::ADD, DL, VT, SHADD, in combineShlAddIAddImpl()