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Searched refs:SETULT (Results 1 – 25 of 64) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchFloat64InstrInfo.td171 // SETOLT/SETOLE/SETULT/SETULE/SETLE/SETEQ/SETLT.
180 def : PatFPSetcc<SETULT, FCMP_CULT_D, FPR64>;
192 defm : PatFPBrcond<SETULT, FCMP_CULT_D, FPR64>;
206 def : PatStrictFsetccs<SETULT, FCMP_SULT_D, FPR64>;
225 def : PatFPSelectcc<SETULT, FCMP_CULT_D, FSEL_xD, FPR64>;
H A DLoongArchFloat32InstrInfo.td195 // SETOLT/SETOLE/SETULT/SETULE/SETLE/SETEQ/SETLT.
204 def : PatFPSetcc<SETULT, FCMP_CULT_S, FPR32>;
224 defm : PatFPBrcond<SETULT, FCMP_CULT_S, FPR32>;
241 def : PatStrictFsetccs<SETULT, FCMP_SULT_S, FPR32>;
264 def : PatFPSelectcc<SETULT, FCMP_CULT_S, FSEL_xS, FPR32>;
H A DLoongArchISelDAGToDAG.h83 case ISD::SETULT: in getBranchOpcForIntCC()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DAnalysis.cpp213 case FCmpInst::FCMP_ULT: return ISD::SETULT; in getFCmpCondCode()
225 case ISD::SETOLT: case ISD::SETULT: return ISD::SETLT; in getFCmpCodeWithoutNaN()
242 case ICmpInst::ICMP_ULT: return ISD::SETULT; in getICmpCondCode()
266 case ISD::SETULT: in getICmpCondCode()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1699 SETULT, // 1 1 0 0 True if unordered or less than enumerator
1725 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; in isUnsignedIntSetCC()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.h85 case ISD::SETULT: in intCondCode2Icc()
129 case ISD::SETULT: in fpCondCode2Fcc()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoXqci.td1446 def : BcciPat<SETULT, QC_BLTUI, uimm5nonzero>;
1453 def : Bcci48Pat<SETULT, QC_E_BLTUI, uimm16nonzero>;
1460 def : SelectQCbi<SETULT, uimm5nonzero, Select_GPRNoX0_Using_CC_UImm5NonZero_QC>;
1467 def : SelectQCbi<SETULT, uimm16nonzero, Select_GPRNoX0_Using_CC_UImm16NonZero_QC>;
1506 def : QCIMVCCPat <SETULT, QC_MVLTU>;
1509 def : QCIMVCCIPat <SETULT, QC_MVLTUI, uimm5>;
1523 def : QCILICCPat <SETULT, QC_LILTU>;
1530 def : QCILICCIPat <SETULT, QC_LILTUI, uimm5>;
1538 def : QCILICCPatInv <SETULT, QC_LIGEU>;
1545 def : QCILICCIPatInv <SETULT, QC_LIGEUI, uimm5>;
H A DRISCVISelDAGToDAG.h190 case ISD::SETULT: in getRISCVCCForIntCC()
H A DRISCVInstrInfoVSDPatterns.td1027 defm : VPatIntegerSetCCSDNode_VV_Swappable<"PseudoVMSLTU", SETULT, SETUGT>;
1034 defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSLTU", SETULT, SETUGT>;
1038 defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSGTU", SETUGT, SETULT>;
1046 defm : VPatIntegerSetCCSDNode_VI_Swappable<"PseudoVMSGTU", SETUGT, SETULT>;
1050 defm : VPatIntegerSetCCSDNode_VI_Swappable<"PseudoVMSLEU", SETULT, SETUGT,
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp3470 case ISD::SETULT: { in get32BitZExtCompare()
3643 case ISD::SETULT: { in get32BitSExtCompare()
3799 case ISD::SETULT: { in get64BitZExtCompare()
3962 case ISD::SETULT: { in get64BitSExtCompare()
4227 case ISD::SETULT: in SelectCC()
4254 case ISD::SETULT: in SelectCC()
4315 case ISD::SETULT: return PPC::PRED_LT; in getPredicateForSetCC()
4347 case ISD::SETULT: return 0; in getCRIdxForSetCC()
4369 case ISD::SETUGT: CC = ISD::SETULT; Swap = true; break; in getVCmpInst()
4377 case ISD::SETULT: CC = ISD::SETOGE; Negate = true; break; in getVCmpInst()
[all …]
H A DPPCInstrInfo.td3567 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)),
3630 // SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for
3810 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)),
3838 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)),
3850 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)),
3878 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)),
4073 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULT)),
4104 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULT)),
4125 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULT)),
4147 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)),
[all …]
H A DPPCInstrSPE.td832 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)),
853 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULT)),
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp393 case ISD::SETULT: in softenSetCCOperands()
4316 if (Cond == ISD::CondCode::SETULT) { in optimizeSetCCOfSignedTruncationCheck()
4503 if (Cond == ISD::SETULT || Cond == ISD::SETUGT) { in simplifySetCCWithCTPOP()
4509 if (C1.ugt(CostLimit + (Cond == ISD::SETULT))) in simplifySetCCWithCTPOP()
4511 if (C1 == 0 && (Cond == ISD::SETULT)) in simplifySetCCWithCTPOP()
4514 unsigned Passes = C1.getLimitedValue() - (Cond == ISD::SETULT); in simplifySetCCWithCTPOP()
4522 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; in simplifySetCCWithCTPOP()
4943 case ISD::SETULT: in SimplifySetCC()
4966 case ISD::SETULT: in SimplifySetCC()
5176 ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT; in SimplifySetCC()
[all …]
H A DLegalizeIntegerTypes.cpp3364 Amt, NVBitsNode, ISD::SETULT); in ExpandShiftWithUnknownAmountBit()
3434 return std::make_pair(ISD::SETULT, ISD::UMIN); in getExpandedMinMaxOps()
3559 Pred = ISD::SETULT; in ExpandIntRes_MINMAX()
3684 ISD::SETULT); in ExpandIntRes_ADDSUB()
3704 LoOps[0], LoOps[1], ISD::SETULT); in ExpandIntRes_ADDSUB()
3777 Cond = ISD::SETULT; in ExpandIntRes_UADDSUBO()
4649 SDValue HLULT = DAG.getSetCC(dl, BoolNVT, ResultHL, HLHiMask, ISD::SETULT); in ExpandIntRes_MULFIX()
5597 case ISD::SETULT: LowCC = ISD::SETULT; break; in IntegerExpandSetCCOperands()
5668 case ISD::SETUGT: CCCode = ISD::SETULT; FlipOperands = true; break; in IntegerExpandSetCCOperands()
H A DSelectionDAGDumper.cpp535 case ISD::SETULT: return "setult"; in getOperationName()
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp666 case ISD::SETULT: in NegateCC()
980 SET_NEWCC(SETULT, JULT); in EmitInstrWithCustomInserter()
H A DBPFInstrInfo.td130 [{return (N->getZExtValue() == ISD::SETULT);}]>;
150 [{return (N->getZExtValue() == ISD::SETULT);}]>;
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrInteger.td77 defm LT_U : ComparisonInt<SETULT, "lt_u", 0x49, 0x54>;
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaISelLowering.cpp832 case ISD::SETULT: in getBranchOpcode()
857 case ISD::SETULT: in getFPBranchKind()
H A DXtensaInstrInfo.td326 def BLTU : Branch_RR<0x03, "bltu", SETULT>;
333 def BLTUI : Branch_RIU<0x0B, "bltui", SETULT>;
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp49 case ISD::SETULT: in ISDCCtoARCCC()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp998 case ISD::SETULT: in isLegalDSPCondCode()
1805 Op->getOperand(2), ISD::SETULT); in lowerINTRINSIC_WO_CHAIN()
1811 lowerMSASplatImm(Op, 2, DAG), ISD::SETULT); in lowerINTRINSIC_WO_CHAIN()
1894 Op->getOperand(2), ISD::SETULT); in lowerINTRINSIC_WO_CHAIN()
H A DMipsMSAInstrInfo.td150 def vfsetult_v4f32 : vfsetcc_type<v4i32, v4f32, SETULT>;
151 def vfsetult_v2f64 : vfsetcc_type<v2i64, v2f64, SETULT>;
178 def vsetult_v16i8 : vsetcc_type<v16i8, SETULT>;
179 def vsetult_v8i16 : vsetcc_type<v8i16, SETULT>;
180 def vsetult_v4i32 : vsetcc_type<v4i32, SETULT>;
181 def vsetult_v2i64 : vsetcc_type<v2i64, SETULT>;
H A DMipsDSPInstrInfo.td1417 def : DSPSetCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>;
1430 def : DSPSelectCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>;
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp270 setCondCodeAction(ISD::SETULT, T, Expand); in initializeHVXLowering()
357 setCondCodeAction(ISD::SETULT, MVT::v64f16, Expand); in initializeHVXLowering()
372 setCondCodeAction(ISD::SETULT, MVT::v32f32, Expand); in initializeHVXLowering()
2447 SDValue Ovf = DAG.getSetCC(dl, PredTy, Add, A, ISD::SETULT); in emitHvxAddWithOverflow()

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