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Searched refs:SETULE (Results 1 – 25 of 59) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchFloat64InstrInfo.td171 // SETOLT/SETOLE/SETULT/SETULE/SETLE/SETEQ/SETLT.
181 def : PatFPSetcc<SETULE, FCMP_CULE_D, FPR64>;
193 defm : PatFPBrcond<SETULE, FCMP_CULE_D, FPR64>;
207 def : PatStrictFsetccs<SETULE, FCMP_SULE_D, FPR64>;
226 def : PatFPSelectcc<SETULE, FCMP_CULE_D, FSEL_xD, FPR64>;
H A DLoongArchFloat32InstrInfo.td195 // SETOLT/SETOLE/SETULT/SETULE/SETLE/SETEQ/SETLT.
205 def : PatFPSetcc<SETULE, FCMP_CULE_S, FPR32>;
225 defm : PatFPBrcond<SETULE, FCMP_CULE_S, FPR32>;
242 def : PatStrictFsetccs<SETULE, FCMP_SULE_S, FPR32>;
265 def : PatFPSelectcc<SETULE, FCMP_CULE_S, FSEL_xS, FPR32>;
H A DLoongArchLASXInstrInfo.td1555 defm : PatCCXrUimm5<SETULE, "XVSLEI">;
1557 defm : PatCCXrXrU<SETULE, "XVSLE">;
1572 defm : PatCCXrXrF<SETULE, "XVFCMP_CULE">;
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DAnalysis.cpp214 case FCmpInst::FCMP_ULE: return ISD::SETULE; in getFCmpCondCode()
226 case ISD::SETOLE: case ISD::SETULE: return ISD::SETLE; in getFCmpCodeWithoutNaN()
238 case ICmpInst::ICMP_ULE: return ISD::SETULE; in getICmpCondCode()
258 case ISD::SETULE: in getICmpCondCode()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1700 SETULE, // 1 1 0 1 True if unordered, less than, or equal enumerator
1725 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; in isUnsignedIntSetCC()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.h87 case ISD::SETULE: in intCondCode2Icc()
133 case ISD::SETULE: in fpCondCode2Fcc()
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp667 case ISD::SETULE: in NegateCC()
982 SET_NEWCC(SETULE, JULE); in EmitInstrWithCustomInserter()
H A DBPFInstrInfo.td132 [{return (N->getZExtValue() == ISD::SETULE);}]>;
152 [{return (N->getZExtValue() == ISD::SETULE);}]>;
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrInteger.td81 defm LE_U : ComparisonInt<SETULE, "le_u", 0x4d, 0x58>;
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp3450 case ISD::SETULE: { in get32BitZExtCompare()
3623 case ISD::SETULE: { in get32BitSExtCompare()
3782 case ISD::SETULE: { in get64BitZExtCompare()
3945 case ISD::SETULE: { in get64BitSExtCompare()
4236 case ISD::SETULE: in SelectCC()
4263 case ISD::SETULE: in SelectCC()
4303 case ISD::SETULE: in getPredicateForSetCC()
4336 case ISD::SETULE: in getCRIdxForSetCC()
4368 case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break; in getVCmpInst()
4376 case ISD::SETULE: CC = ISD::SETOGT; Negate = true; break; in getVCmpInst()
[all …]
H A DPPCInstrInfo.td3588 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULE)),
3895 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULE)),
3912 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETULE)),
3924 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULE)),
3941 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETULE)),
3954 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)),
4026 defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETULE)),
4053 defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETULE)),
4079 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULE)),
4108 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULE)),
[all …]
H A DPPCInstrSPE.td836 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULE)),
857 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULE)),
H A DPPCInstrP10.td1981 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)),
1992 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, ZExtTy:$imm, SETULE)),
2007 defm : P10ReverseSetBool<(i1 (SetCC Ty:$s1, Ty:$s2, SETULE)),
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaISelLowering.cpp133 setCondCodeAction(ISD::SETULE, MVT::i32, Expand); in XtensaTargetLowering()
834 case ISD::SETULE: in getBranchOpcode()
855 case ISD::SETULE: in getFPBranchKind()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVSDPatterns.td1029 defm : VPatIntegerSetCCSDNode_VV_Swappable<"PseudoVMSLEU", SETULE, SETUGE>;
1036 defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSLEU", SETULE, SETUGE>;
1044 defm : VPatIntegerSetCCSDNode_VI_Swappable<"PseudoVMSLEU", SETULE, SETUGE>;
1054 defm : VPatIntegerSetCCSDNode_VI_Swappable<"PseudoVMSGTU", SETUGE, SETULE,
H A DRISCVInstrInfoVVLPatterns.td2274 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>;
2281 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>;
2289 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>;
2299 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSGTU", SETUGE, SETULE,
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp398 case ISD::SETULE: in softenSetCCOperands()
4318 } else if (Cond == ISD::CondCode::SETULE) { in optimizeSetCCOfSignedTruncationCheck()
4550 ISD::CondCode CmpCond = Cond == ISD::SETEQ ? ISD::SETUGT : ISD::SETULE; in simplifySetCCWithCTPOP()
4944 case ISD::SETULE: in SimplifySetCC()
4967 case ISD::SETULE: { in SimplifySetCC()
5168 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { in SimplifySetCC()
5308 (Cond == ISD::SETULE && C1.isMaxSignedValue())) in SimplifySetCC()
5374 Cond == ISD::SETULE || Cond == ISD::SETUGT) { in SimplifySetCC()
5375 bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT); in SimplifySetCC()
5386 NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; in SimplifySetCC()
[all …]
H A DSelectionDAGDumper.cpp536 case ISD::SETULE: return "setule"; in getOperationName()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp51 case ISD::SETULE: in ISDCCtoARCCC()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp999 case ISD::SETULE: in isLegalDSPCondCode()
1781 Op->getOperand(2), ISD::SETULE); in lowerINTRINSIC_WO_CHAIN()
1787 lowerMSASplatImm(Op, 2, DAG), ISD::SETULE); in lowerINTRINSIC_WO_CHAIN()
1890 Op->getOperand(2), ISD::SETULE); in lowerINTRINSIC_WO_CHAIN()
H A DMipsMSAInstrInfo.td148 def vfsetule_v4f32 : vfsetcc_type<v4i32, v4f32, SETULE>;
149 def vfsetule_v2f64 : vfsetcc_type<v2i64, v2f64, SETULE>;
174 def vsetule_v16i8 : vsetcc_type<v16i8, SETULE>;
175 def vsetule_v8i16 : vsetcc_type<v8i16, SETULE>;
176 def vsetule_v4i32 : vsetcc_type<v4i32, SETULE>;
177 def vsetule_v2i64 : vsetcc_type<v2i64, SETULE>;
H A DMipsDSPInstrInfo.td1418 def : DSPSetCCPat<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETULE>;
1431 def : DSPSelectCCPat<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETULE>;
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp88 ISD::SETUGT, ISD::SETULT, ISD::SETULE}, in R600TargetLowering()
91 setCondCodeAction({ISD::SETLE, ISD::SETLT, ISD::SETULE, ISD::SETULT}, in R600TargetLowering()
H A DAMDGPUInstructions.td366 def COND_ULE : PatFrag<(ops), (OtherVT SETULE)>;
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp268 setCondCodeAction(ISD::SETULE, T, Expand); in initializeHVXLowering()
355 setCondCodeAction(ISD::SETULE, MVT::v64f16, Expand); in initializeHVXLowering()
370 setCondCodeAction(ISD::SETULE, MVT::v32f32, Expand); in initializeHVXLowering()

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