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Searched refs:SETUGT (Results 1 – 25 of 58) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DAnalysis.cpp211 case FCmpInst::FCMP_UGT: return ISD::SETUGT; in getFCmpCondCode()
227 case ISD::SETOGT: case ISD::SETUGT: return ISD::SETGT; in getFCmpCodeWithoutNaN()
244 case ICmpInst::ICMP_UGT: return ISD::SETUGT; in getICmpCondCode()
270 case ISD::SETUGT: in getICmpCondCode()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1697 SETUGT, // 1 0 1 0 True if unordered or greater than enumerator
1725 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; in isUnsignedIntSetCC()
H A DSDPatternMatch.h718 return Cond == ISD::CondCode::SETUGT || Cond == ISD::CondCode::SETUGE;
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.h89 case ISD::SETUGT: in intCondCode2Icc()
131 case ISD::SETUGT: in fpCondCode2Fcc()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp3465 case ISD::SETUGT: in get32BitZExtCompare()
3638 case ISD::SETUGT: in get32BitSExtCompare()
3794 case ISD::SETUGT: in get64BitZExtCompare()
3957 case ISD::SETUGT: in get64BitSExtCompare()
4235 case ISD::SETUGT: in SelectCC()
4262 case ISD::SETUGT: in SelectCC()
4316 case ISD::SETUGT: return PPC::PRED_GT; in getPredicateForSetCC()
4348 case ISD::SETUGT: return 1; in getCRIdxForSetCC()
4369 case ISD::SETUGT: CC = ISD::SETULT; Swap = true; break; in getVCmpInst()
4413 case ISD::SETULT: CC = ISD::SETUGT; Swap = true; break; in getVCmpInst()
[all …]
H A DPPCInstrInfo.td3623 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)),
3630 // SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for
3814 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGT)),
3842 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETUGT)),
3854 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGT)),
3882 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETUGT)),
4094 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGT)),
4118 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGT)),
4139 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETUGT)),
4161 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGT)),
[all …]
H A DPPCInstrSPE.td846 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGT)),
867 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGT)),
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrInteger.td79 defm GT_U : ComparisonInt<SETUGT, "gt_u", 0x4b, 0x56>;
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp403 case ISD::SETUGT: in softenSetCCOperands()
4322 } else if (Cond == ISD::CondCode::SETUGT) { in optimizeSetCCOfSignedTruncationCheck()
4503 if (Cond == ISD::SETULT || Cond == ISD::SETUGT) { in simplifySetCCWithCTPOP()
4550 ISD::CondCode CmpCond = Cond == ISD::SETEQ ? ISD::SETUGT : ISD::SETULE; in simplifySetCCWithCTPOP()
4939 case ISD::SETUGT: in SimplifySetCC()
4964 case ISD::SETUGT: in SimplifySetCC()
5156 ISD::CondCode NewCC = (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT; in SimplifySetCC()
5206 if (Cond == ISD::SETGT || Cond == ISD::SETUGT) { in SimplifySetCC()
5299 if ((Cond == ISD::SETUGT && C1.isMaxSignedValue()) || in SimplifySetCC()
5374 Cond == ISD::SETULE || Cond == ISD::SETUGT) { in SimplifySetCC()
[all …]
H A DSelectionDAGDumper.cpp533 case ISD::SETUGT: return "setugt"; in getOperationName()
H A DLegalizeIntegerTypes.cpp3430 return std::make_pair(ISD::SETUGT, ISD::UMAX); in getExpandedMinMaxOps()
3553 Pred = ISD::SETUGT; in ExpandIntRes_MINMAX()
3782 Cond = ISD::SETUGT; in ExpandIntRes_UADDSUBO()
4643 SDValue HLUGT = DAG.getSetCC(dl, BoolNVT, ResultHL, HLLoMask, ISD::SETUGT); in ExpandIntRes_MULFIX()
5599 case ISD::SETUGT: LowCC = ISD::SETUGT; break; in IntegerExpandSetCCOperands()
5668 case ISD::SETUGT: CCCode = ISD::SETULT; FlipOperands = true; break; in IntegerExpandSetCCOperands()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVSDPatterns.td1027 defm : VPatIntegerSetCCSDNode_VV_Swappable<"PseudoVMSLTU", SETULT, SETUGT>;
1034 defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSLTU", SETULT, SETUGT>;
1038 defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSGTU", SETUGT, SETULT>;
1046 defm : VPatIntegerSetCCSDNode_VI_Swappable<"PseudoVMSGTU", SETUGT, SETULT>;
1050 defm : VPatIntegerSetCCSDNode_VI_Swappable<"PseudoVMSLEU", SETULT, SETUGT,
H A DRISCVInstrInfoVVLPatterns.td2272 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLTU", SETULT, SETUGT>;
2279 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLTU", SETULT, SETUGT>;
2283 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSGTU", SETUGT, SETULT>;
2291 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSGTU", SETUGT, SETULT>;
2295 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSLEU", SETULT, SETUGT,
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaISelLowering.cpp132 setCondCodeAction(ISD::SETUGT, MVT::i32, Expand); in XtensaTargetLowering()
836 case ISD::SETUGT: in getBranchOpcode()
880 case ISD::SETUGT: in getFPBranchKind()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchFloat64InstrInfo.td170 // SETOGT/SETOGE/SETUGT/SETUGE/SETGE/SETNE/SETGT will expand into
H A DLoongArchFloat32InstrInfo.td194 // SETOGT/SETOGE/SETUGT/SETUGE/SETGE/SETNE/SETGT will expand into
H A DLoongArchISelLowering.cpp179 ISD::SETOGT, ISD::SETOGE, ISD::SETUGT, ISD::SETUGE, in LoongArchTargetLowering()
307 {ISD::SETNE, ISD::SETGE, ISD::SETGT, ISD::SETUGE, ISD::SETUGT}, VT, in LoongArchTargetLowering()
328 ISD::SETUGE, ISD::SETUGT}, in LoongArchTargetLowering()
374 {ISD::SETNE, ISD::SETGE, ISD::SETGT, ISD::SETUGE, ISD::SETUGT}, VT, in LoongArchTargetLowering()
395 ISD::SETUGE, ISD::SETUGT}, in LoongArchTargetLowering()
754 case ISD::SETUGT: in translateSetCCForBranch()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp302 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand); in MipsSETargetLowering()
307 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand); in MipsSETargetLowering()
403 setCondCodeAction(ISD::SETUGT, Ty, Expand); in addMSAIntType()
439 setCondCodeAction(ISD::SETUGT, Ty, Expand); in addMSAFloatType()
1000 case ISD::SETUGT: in isLegalDSPCondCode()
H A DMipsDSPInstrInfo.td1421 def : DSPSetCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>;
1434 def : DSPSelectCCPatInv<PseudoCMPU_LE_QB, PseudoPICK_QB, v4i8, SETUGT>;
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp45 case ISD::SETUGT: in ISDCCtoARCCC()
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFInstrInfo.td122 [{return (N->getZExtValue() == ISD::SETUGT);}]>;
142 [{return (N->getZExtValue() == ISD::SETUGT);}]>;
H A DBPFISelLowering.cpp974 SET_NEWCC(SETUGT, JUGT); in EmitInstrWithCustomInserter()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp1745 case ISD::SETUGT: in TranslateIntegerM68kCC()
1792 case ISD::SETUGT: in TranslateM68kCC()
1818 case ISD::SETUGT: // flipped in TranslateM68kCC()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructions.td363 def COND_UGT : PatFrag<(ops), (OtherVT SETUGT)>;
H A DSIWholeQuadMode.cpp828 case ISD::SETUGT: in lowerKillF32()

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