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Searched refs:SETUGE (Results 1 – 25 of 62) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DAnalysis.cpp212 case FCmpInst::FCMP_UGE: return ISD::SETUGE; in getFCmpCondCode()
228 case ISD::SETOGE: case ISD::SETUGE: return ISD::SETGE; in getFCmpCodeWithoutNaN()
240 case ICmpInst::ICMP_UGE: return ISD::SETUGE; in getICmpCondCode()
262 case ISD::SETUGE: in getICmpCondCode()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelDAGToDAG.h85 case ISD::SETUGE: in getBranchOpcForIntCC()
H A DLoongArchFloat64InstrInfo.td170 // SETOGT/SETOGE/SETUGT/SETUGE/SETGE/SETNE/SETGT will expand into
H A DLoongArchFloat32InstrInfo.td194 // SETOGT/SETOGE/SETUGT/SETUGE/SETGE/SETNE/SETGT will expand into
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1698 SETUGE, // 1 0 1 1 True if unordered, greater than, or equal enumerator
1725 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; in isUnsignedIntSetCC()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.h91 case ISD::SETUGE: in intCondCode2Icc()
135 case ISD::SETUGE: in fpCondCode2Fcc()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.h192 case ISD::SETUGE: in getRISCVCCForIntCC()
H A DRISCVInstrInfoXqci.td1447 def : BcciPat<SETUGE, QC_BGEUI, uimm5nonzero>;
1454 def : Bcci48Pat<SETUGE, QC_E_BGEUI, uimm16nonzero>;
1461 def : SelectQCbi<SETUGE, uimm5nonzero, Select_GPRNoX0_Using_CC_UImm5NonZero_QC>;
1468 def : SelectQCbi<SETUGE, uimm16nonzero, Select_GPRNoX0_Using_CC_UImm16NonZero_QC>;
1524 def : QCILICCPat <SETUGE, QC_LIGEU>;
1531 def : QCILICCIPat <SETUGE, QC_LIGEUI, uimm5>;
1537 def : QCILICCPatInv <SETUGE, QC_LILTU>;
1544 def : QCILICCIPatInv <SETUGE, QC_LILTUI, uimm5>;
H A DRISCVInstrInfoVSDPatterns.td1029 defm : VPatIntegerSetCCSDNode_VV_Swappable<"PseudoVMSLEU", SETULE, SETUGE>;
1036 defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSLEU", SETULE, SETUGE>;
1044 defm : VPatIntegerSetCCSDNode_VI_Swappable<"PseudoVMSLEU", SETULE, SETUGE>;
1054 defm : VPatIntegerSetCCSDNode_VI_Swappable<"PseudoVMSGTU", SETUGE, SETULE,
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrInteger.td83 defm GE_U : ComparisonInt<SETUGE, "ge_u", 0x4f, 0x5a>;
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.td3607 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)),
3891 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)),
3908 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)),
3920 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)),
3937 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)),
3950 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)),
4022 defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETUGE)),
4049 defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETUGE)),
4088 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGE)),
4114 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGE)),
[all …]
H A DPPCISelDAGToDAG.cpp3445 case ISD::SETUGE: in get32BitZExtCompare()
3618 case ISD::SETUGE: in get32BitSExtCompare()
3777 case ISD::SETUGE: in get64BitZExtCompare()
3940 case ISD::SETUGE: in get64BitSExtCompare()
4228 case ISD::SETUGE: in SelectCC()
4255 case ISD::SETUGE: in SelectCC()
4309 case ISD::SETUGE: in getPredicateForSetCC()
4334 case ISD::SETUGE: in getCRIdxForSetCC()
4368 case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break; in getVCmpInst()
4412 case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break; in getVCmpInst()
H A DPPCInstrSPE.td842 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGE)),
863 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGE)),
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp1696 case ISD::SETUGE: in combineFMinMaxLegacyImpl()
2194 ISD::SETUGE); in LowerUDIVREM64()
2196 ISD::SETUGE); in LowerUDIVREM64()
2216 ISD::SETUGE); in LowerUDIVREM64()
2218 ISD::SETUGE); in LowerUDIVREM64()
2276 SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, Zero, ISD::SETUGE); in LowerUDIVREM64()
2282 REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETUGE); in LowerUDIVREM64()
2330 SDValue Cond = DAG.getSetCC(DL, CCVT, R, Y, ISD::SETUGE); in LowerUDIVREM()
2337 Cond = DAG.getSetCC(DL, CCVT, R, Y, ISD::SETUGE); in LowerUDIVREM()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp301 setCondCodeAction(ISD::SETUGE, MVT::f32, Expand); in MipsSETargetLowering()
306 setCondCodeAction(ISD::SETUGE, MVT::f64, Expand); in MipsSETargetLowering()
402 setCondCodeAction(ISD::SETUGE, Ty, Expand); in addMSAIntType()
438 setCondCodeAction(ISD::SETUGE, Ty, Expand); in addMSAFloatType()
1001 case ISD::SETUGE: return !IsV216; in isLegalDSPCondCode()
H A DMipsDSPInstrInfo.td1420 def : DSPSetCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>;
1433 def : DSPSelectCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>;
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp408 case ISD::SETUGE: in softenSetCCOperands()
4326 } else if (Cond == ISD::CondCode::SETUGE) { in optimizeSetCCOfSignedTruncationCheck()
4940 case ISD::SETUGE: in SimplifySetCC()
4965 case ISD::SETUGE: in SimplifySetCC()
5148 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { in SimplifySetCC()
5300 (Cond == ISD::SETUGE && C1.isMinSignedValue())) in SimplifySetCC()
5373 } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE || in SimplifySetCC()
5386 NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; in SimplifySetCC()
5451 case ISD::SETUEQ: NewCond = IsNegInf ? ISD::SETULE : ISD::SETUGE; break; in SimplifySetCC()
5632 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X in SimplifySetCC()
[all …]
H A DSelectionDAGDumper.cpp534 case ISD::SETUGE: return "setuge"; in getOperationName()
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp571 case ISD::SETUGE: in intCCToAVRCC()
709 CC = ISD::SETUGE; in getAVRCmp()
720 CC = ISD::SETUGE; in getAVRCmp()
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaISelLowering.cpp838 case ISD::SETUGE: in getBranchOpcode()
882 case ISD::SETUGE: in getFPBranchKind()
H A DXtensaInstrInfo.td325 def BGEU : Branch_RR<0x0B, "bgeu", SETUGE>;
332 def BGEUI : Branch_RIU<0x0F, "bgeui", SETUGE>;
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp47 case ISD::SETUGE: in ISDCCtoARCCC()
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFInstrInfo.td124 [{return (N->getZExtValue() == ISD::SETUGE);}]>;
144 [{return (N->getZExtValue() == ISD::SETUGE);}]>;
H A DBPFISelLowering.cpp976 SET_NEWCC(SETUGE, JUGE); in EmitInstrWithCustomInserter()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp1743 case ISD::SETUGE: in TranslateIntegerM68kCC()
1793 case ISD::SETUGE: in TranslateM68kCC()
1822 case ISD::SETUGE: // flipped in TranslateM68kCC()

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