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Searched refs:SETUGE (Results 1 – 25 of 56) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DAnalysis.cpp212 case FCmpInst::FCMP_UGE: return ISD::SETUGE; in getFCmpCondCode()
228 case ISD::SETOGE: case ISD::SETUGE: return ISD::SETGE; in getFCmpCodeWithoutNaN()
240 case ICmpInst::ICMP_UGE: return ISD::SETUGE; in getICmpCondCode()
262 case ISD::SETUGE: in getICmpCondCode()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1587 SETUGE, // 1 0 1 1 True if unordered, greater than, or equal enumerator
1614 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; in isUnsignedIntSetCC()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.h183 case ISD::SETUGE: in getRISCVCCForIntCC()
H A DRISCVInstrInfoVSDPatterns.td1030 defm : VPatIntegerSetCCSDNode_VV_Swappable<"PseudoVMSLEU", SETULE, SETUGE>;
1037 defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSLEU", SETULE, SETUGE>;
1045 defm : VPatIntegerSetCCSDNode_VI_Swappable<"PseudoVMSLEU", SETULE, SETUGE>;
1055 defm : VPatIntegerSetCCSDNode_VIPlus1_Swappable<"PseudoVMSGTU", SETUGE, SETULE,
H A DRISCVInstrInfoVVLPatterns.td2322 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>;
2329 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>;
2337 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>;
2347 defm : VPatIntegerSetCCVL_VIPlus1_Swappable<vti, "PseudoVMSGTU", SETUGE, SETULE,
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaInstrInfo.td326 def BGEU : Branch_RR<0x0B, "bgeu", SETUGE>;
333 def BGEUI : Branch_RIU<0x0F, "bgeui", SETUGE>;
H A DXtensaISelLowering.cpp545 case ISD::SETUGE: in getBranchOpcode()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrInteger.td83 defm GE_U : ComparisonInt<SETUGE, "ge_u", 0x4f, 0x5a>;
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchFloat32InstrInfo.td188 // SETOGT/SETOGE/SETUGT/SETUGE/SETGE/SETNE/SETGT will expand into
H A DLoongArchFloat64InstrInfo.td168 // SETOGT/SETOGE/SETUGT/SETUGE/SETGE/SETNE/SETGT will expand into
H A DLoongArchISelLowering.cpp160 ISD::SETOGT, ISD::SETOGE, ISD::SETUGT, ISD::SETUGE, in LoongArchTargetLowering()
268 {ISD::SETNE, ISD::SETGE, ISD::SETGT, ISD::SETUGE, ISD::SETUGT}, VT, in LoongArchTargetLowering()
282 ISD::SETUGE, ISD::SETUGT}, in LoongArchTargetLowering()
315 {ISD::SETNE, ISD::SETGE, ISD::SETGT, ISD::SETUGE, ISD::SETUGT}, VT, in LoongArchTargetLowering()
329 ISD::SETUGE, ISD::SETUGT}, in LoongArchTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.td3567 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGE)),
3851 defm : CRNotPat<(i1 (setcc i32:$s1, immZExt16:$imm, SETUGE)),
3868 defm : CRNotPat<(i1 (setcc i32:$s1, i32:$s2, SETUGE)),
3880 defm : CRNotPat<(i1 (setcc i64:$s1, immZExt16:$imm, SETUGE)),
3897 defm : CRNotPat<(i1 (setcc i64:$s1, i64:$s2, SETUGE)),
3910 defm : CRNotPat<(i1 (SetCC Ty:$s1, Ty:$s2, SETUGE)),
3982 defm : CRNotPat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETUGE)),
4009 defm : CRNotPat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETUGE)),
4048 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETUGE)),
4074 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETUGE)),
[all …]
H A DPPCISelDAGToDAG.cpp3446 case ISD::SETUGE: in get32BitZExtCompare()
3619 case ISD::SETUGE: in get32BitSExtCompare()
3778 case ISD::SETUGE: in get64BitZExtCompare()
3941 case ISD::SETUGE: in get64BitSExtCompare()
4229 case ISD::SETUGE: in SelectCC()
4256 case ISD::SETUGE: in SelectCC()
4310 case ISD::SETUGE: in getPredicateForSetCC()
4335 case ISD::SETUGE: in getCRIdxForSetCC()
4369 case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break; in getVCmpInst()
4413 case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break; in getVCmpInst()
H A DPPCInstrSPE.td842 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETUGE)),
863 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETUGE)),
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp1639 case ISD::SETUGE: in combineFMinMaxLegacyImpl()
2137 ISD::SETUGE); in LowerUDIVREM64()
2139 ISD::SETUGE); in LowerUDIVREM64()
2159 ISD::SETUGE); in LowerUDIVREM64()
2161 ISD::SETUGE); in LowerUDIVREM64()
2219 SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, Zero, ISD::SETUGE); in LowerUDIVREM64()
2225 REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETUGE); in LowerUDIVREM64()
2273 SDValue Cond = DAG.getSetCC(DL, CCVT, R, Y, ISD::SETUGE); in LowerUDIVREM()
2280 Cond = DAG.getSetCC(DL, CCVT, R, Y, ISD::SETUGE); in LowerUDIVREM()
H A DAMDGPUInstructions.td364 def COND_UGE : PatFrag<(ops), (OtherVT SETUGE)>;
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp262 setCondCodeAction(ISD::SETUGE, MVT::f32, Expand); in MipsSETargetLowering()
267 setCondCodeAction(ISD::SETUGE, MVT::f64, Expand); in MipsSETargetLowering()
363 setCondCodeAction(ISD::SETUGE, Ty, Expand); in addMSAIntType()
399 setCondCodeAction(ISD::SETUGE, Ty, Expand); in addMSAFloatType()
962 case ISD::SETUGE: return !IsV216; in isLegalDSPCondCode()
H A DMipsDSPInstrInfo.td1420 def : DSPSetCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>;
1433 def : DSPSelectCCPatInv<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETUGE>;
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp628 case ISD::SETUGE: in intCCToAVRCC()
766 CC = ISD::SETUGE; in getAVRCmp()
774 CC = ISD::SETUGE; in getAVRCmp()
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFInstrInfo.td123 [{return (N->getZExtValue() == ISD::SETUGE);}]>;
143 [{return (N->getZExtValue() == ISD::SETUGE);}]>;
H A DBPFISelLowering.cpp868 SET_NEWCC(SETUGE, JUGE); in EmitInstrWithCustomInserter()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp46 case ISD::SETUGE: in ISDCCtoARCCC()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp512 case ISD::SETUGE: return "setuge"; in getOperationName()
H A DTargetLowering.cpp394 case ISD::SETUGE: in softenSetCCOperands()
4114 } else if (Cond == ISD::CondCode::SETUGE) { in optimizeSetCCOfSignedTruncationCheck()
4726 case ISD::SETUGE: in SimplifySetCC()
4751 case ISD::SETUGE: in SimplifySetCC()
4932 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { in SimplifySetCC()
5084 (Cond == ISD::SETUGE && C1.isMinSignedValue())) in SimplifySetCC()
5159 } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE || in SimplifySetCC()
5172 NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; in SimplifySetCC()
5237 case ISD::SETUEQ: NewCond = IsNegInf ? ISD::SETULE : ISD::SETUGE; break; in SimplifySetCC()
5415 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X in SimplifySetCC()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp1741 case ISD::SETUGE: in TranslateIntegerM68kCC()
1791 case ISD::SETUGE: in TranslateM68kCC()
1820 case ISD::SETUGE: // flipped in TranslateM68kCC()

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