| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchFloat32InstrInfo.td | 197 def : PatFPSetcc<SETUEQ, FCMP_CUEQ_S, FPR32>;
217 defm : PatFPBrcond<SETUEQ, FCMP_CUEQ_S, FPR32>;
234 def : PatStrictFsetccs<SETUEQ, FCMP_SUEQ_S, FPR32>;
257 def : PatFPSelectcc<SETUEQ, FCMP_CUEQ_S, FSEL_xS, FPR32>;
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| H A D | LoongArchFloat64InstrInfo.td | 177 def : PatFPSetcc<SETUEQ, FCMP_CUEQ_D, FPR64>;
189 defm : PatFPBrcond<SETUEQ, FCMP_CUEQ_D, FPR64>;
203 def : PatStrictFsetccs<SETUEQ, FCMP_SUEQ_D, FPR64>;
222 def : PatFPSelectcc<SETUEQ, FCMP_CUEQ_D, FSEL_xD, FPR64>;
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| H A D | LoongArchLASXInstrInfo.td | 1524 defm : PatCCXrXrF<SETUEQ, "XVFCMP_CUEQ">;
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| H A D | LoongArchLSXInstrInfo.td | 1646 defm : PatCCVrVrF<SETUEQ, "VFCMP_CUEQ">;
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 1585 SETUEQ, // 1 0 0 1 True if unordered or equal enumerator
1626 return Code == SETOEQ || Code == SETONE || Code == SETUEQ || Code == SETUNE; in isFPEqualitySetCC()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | Analysis.cpp | 210 case FCmpInst::FCMP_UEQ: return ISD::SETUEQ; in getFCmpCondCode()
223 case ISD::SETOEQ: case ISD::SETUEQ: return ISD::SETEQ; in getFCmpCodeWithoutNaN()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructions.td | 361 def COND_UEQ : PatFrag<(ops), (OtherVT SETUEQ)>;
385 def COND_EQ : PatFrags<(ops), [(OtherVT SETEQ), (OtherVT SETUEQ)]>;
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| H A D | SIWholeQuadMode.cpp | 815 case ISD::SETUEQ: in lowerKillF32()
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| H A D | R600ISelLowering.cpp | 88 ISD::SETOLE, ISD::SETONE, ISD::SETUEQ, ISD::SETUGE, in R600TargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCISelLowering.cpp | 42 case ISD::SETUEQ: in ISDCCtoARCCC()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 510 case ISD::SETUEQ: return "setueq"; in getOperationName()
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| H A D | TargetLowering.cpp | 367 case ISD::SETUEQ: in softenSetCCOperands()
5216 if ((Cond == ISD::SETOEQ || Cond == ISD::SETUEQ) && CFP->isInfinity()) { in SimplifySetCC()
5219 if (Cond == ISD::SETUEQ) in SimplifySetCC()
5237 case ISD::SETUEQ: NewCond = IsNegInf ? ISD::SETULE : ISD::SETUGE; break; in SimplifySetCC()
8598 ISD::CondCode UnorderedCmpOpcode = IsInverted ? ISD::SETONE : ISD::SETUEQ; in expandIS_FPCLASS()
11284 DAG.getSetCC(dl, WideSetCCVT, AbsWide, AbsNarrowAsWide, ISD::SETUEQ); in expandRoundInexactToOdd()
11601 case ISD::SETUEQ: in LegalizeSetCCCondCode()
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| H A D | SelectionDAG.cpp | 668 case ISD::SETUEQ: Result = ISD::SETEQ ; break; // SETUGE & SETULE in getSetCCAndOperation()
2557 case ISD::SETUEQ: in FoldSetCC()
2636 case ISD::SETUEQ: return getBoolConstant(R==APFloat::cmpUnordered || in FoldSetCC()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelLowering.cpp | 115 ISD::SETONE, ISD::SETUEQ, ISD::SETUGT, in CSKYTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.cpp | 859 case ISD::SETUEQ: in IntCondCCodeToICC()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelDAGToDAG.cpp | 4289 case ISD::SETUEQ: in getPredicateForSetCC()
4342 case ISD::SETUEQ: in getCRIdxForSetCC()
4420 case ISD::SETUNE: CC = ISD::SETUEQ; Negate = true; break; in getVCmpInst()
4428 case ISD::SETUEQ: in getVCmpInst()
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| H A D | PPCISelLowering.cpp | 678 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand); in PPCTargetLowering()
679 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand); in PPCTargetLowering()
996 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand); in PPCTargetLowering()
1049 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand); in PPCTargetLowering()
1229 setCondCodeAction(ISD::SETUEQ, MVT::f128, Expand); in PPCTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 857 def SETUEQ : CondCode<"FCMP_UEQ">;
1499 (setcc node:$lhs, node:$rhs, SETUEQ)>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 127 for (auto CC : {ISD::SETO, ISD::SETUO, ISD::SETUEQ, ISD::SETONE, in WebAssemblyTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsMSAInstrInfo.td | 142 def vfsetueq_v4f32 : vfsetcc_type<v4i32, v4f32, SETUEQ>;
143 def vfsetueq_v2f64 : vfsetcc_type<v2i64, v2f64, SETUEQ>;
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| H A D | MipsSEISelLowering.cpp | 1842 Op->getOperand(2), ISD::SETUEQ); in lowerINTRINSIC_WO_CHAIN()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 1805 case ISD::SETUEQ: in TranslateM68kCC()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelDAGToDAG.cpp | 596 case ISD::SETUEQ: in getPTXCmpMode()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1578 case ISD::SETUEQ: return SPCC::FCC_UE; in FPCondCCodeToFCC()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1652 setCondCodeAction(ISD::SETUEQ, VT, Expand); in AArch64TargetLowering()
2000 setCondCodeAction(ISD::SETUEQ, VT, Expand); in addTypeForFixedLengthSVE()
3315 case ISD::SETUEQ: in changeFPCCToAArch64CC()
3359 case ISD::SETUEQ: in changeFPCCToANDAArch64CC()
3390 case ISD::SETUEQ: in changeVectorFPCCToAArch64CC()
10628 if ((CC == ISD::SETEQ || CC == ISD::SETOEQ || CC == ISD::SETUEQ) && in LowerSELECT_CC()
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