/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
H A D | CSKYInstrInfoF2.td | 383 defm : BRCond_Bin_SWAP_F2<SETOGT, "f2FCMPLT", BT32, BF32, MVC32>; 414 def : Pat<(brcond (i32 (setcc FPR32Op:$rs1, fpimm0, SETOGT)), bb:$imm16), 416 def : Pat<(i32 (setcc FPR32Op:$rs1, fpimm0, SETOGT)), 418 def : Pat<(select (i32 (setcc FPR32Op:$rs1, fpimm0, SETOGT)), FPR32Op:$rx, FPR32Op:$false),
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H A D | CSKYInstrInfoF1.td | 363 defm : BRCond_Bin_SWAP<SETOGT, "FCMPLT", BT32, BF32, MVC32>; 388 def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETOGT)), bb:$imm16), 390 def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETOGT)),
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | Analysis.cpp | 203 case FCmpInst::FCMP_OGT: return ISD::SETOGT; in getFCmpCondCode() 227 case ISD::SETOGT: case ISD::SETUGT: return ISD::SETGT; in getFCmpCodeWithoutNaN()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | ISDOpcodes.h | 1578 SETOGT, // 0 0 1 0 True if ordered and greater than enumerator
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/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyInstrFloat.td | 89 defm GT : ComparisonFP<SETOGT, "gt ", 0x5e, 0x64>;
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H A D | WebAssemblyInstrSIMD.td | 774 defm GT : SIMDConditionFP<"gt", SETOGT, 68>;
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/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
H A D | LoongArchFloat32InstrInfo.td | 188 // SETOGT/SETOGE/SETUGT/SETUGE/SETGE/SETNE/SETGT will expand into
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H A D | LoongArchFloat64InstrInfo.td | 168 // SETOGT/SETOGE/SETUGT/SETUGE/SETGE/SETNE/SETGT will expand into
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H A D | LoongArchISelLowering.cpp | 160 ISD::SETOGT, ISD::SETOGE, ISD::SETUGT, ISD::SETUGE, in LoongArchTargetLowering() 281 setCondCodeAction({ISD::SETGE, ISD::SETGT, ISD::SETOGE, ISD::SETOGT, in LoongArchTargetLowering() 328 setCondCodeAction({ISD::SETGE, ISD::SETGT, ISD::SETOGE, ISD::SETOGT, in LoongArchTargetLowering()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAGDumper.cpp | 502 case ISD::SETOGT: return "setogt"; in getOperationName()
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H A D | TargetLowering.cpp | 350 case ISD::SETOGT: in softenSetCCOperands() 5239 case ISD::SETONE: NewCond = IsNegInf ? ISD::SETOGT : ISD::SETOLT; break; in SimplifySetCC() 11223 SDValue OGT = DAG.getSetCC(dl, SetCCVT, Src, MaxFloatNode, ISD::SETOGT); in expandFP_TO_INT_SAT() 11289 DAG.getSetCC(dl, WideSetCCVT, AbsWide, AbsNarrowAsWide, ISD::SETOGT); in expandRoundInexactToOdd() 11608 (TLI.isCondCodeLegal(ISD::SETOGT, OpVT) || in LegalizeSetCCCondCode() 11610 CC1 = ISD::SETOGT; in LegalizeSetCCCondCode() 11618 case ISD::SETOGT: in LegalizeSetCCCondCode()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 4234 case ISD::SETOGT: in SelectCC() 4261 case ISD::SETOGT: in SelectCC() 4307 case ISD::SETOGT: in getPredicateForSetCC() 4330 case ISD::SETOGT: in getCRIdxForSetCC() 4368 case ISD::SETOLT: CC = ISD::SETOGT; Swap = true; break; in getVCmpInst() 4377 case ISD::SETULE: CC = ISD::SETOGT; Negate = true; break; in getVCmpInst() 4391 case ISD::SETOGT: in getVCmpInst()
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H A D | PPCInstrInfo.td | 3929 def : Pat<(i1 (SetCC Ty:$s1, Ty:$s2, SETOGT)), 3973 def : Pat<(i1 (any_fsetccs f32:$s1, f32:$s2, SETOGT)), 4000 def : Pat<(i1 (any_fsetccs f64:$s1, f64:$s2, SETOGT)),
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUInstructions.td | 350 def COND_OGT : PatFrags<(ops), [(OtherVT SETOGT), (OtherVT SETGT)]>;
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H A D | SIWholeQuadMode.cpp | 843 case ISD::SETOGT: in lowerKillF32()
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H A D | AMDGPUISelLowering.cpp | 1648 case ISD::SETOGT: { in combineFMinMaxLegacyImpl() 2380 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOGT); in LowerFCEIL() 2473 SDValue Cond = DAG.getSetCC(SL, SetCCVT, Fabs, C2, ISD::SETOGT); in LowerFROUNDEVEN() 3099 DAG.getSetCC(SL, SetCCVT, X, OverflowCheckConst, ISD::SETOGT); in lowerFEXP()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 261 setCondCodeAction(ISD::SETOGT, MVT::f32, Expand); in MipsSETargetLowering() 266 setCondCodeAction(ISD::SETOGT, MVT::f64, Expand); in MipsSETargetLowering() 398 setCondCodeAction(ISD::SETOGT, Ty, Expand); in addMSAFloatType()
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H A D | MipsMSAInstrInfo.td | 130 def vfsetogt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGT>; 131 def vfsetogt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGT>;
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/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
H A D | LanaiISelLowering.cpp | 857 case ISD::SETOGT: in IntCondCCodeToICC()
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/freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
H A D | TargetSelectionDAG.td | 850 def SETOGT : CondCode<"FCMP_OGT">; 1485 (setcc node:$lhs, node:$rhs, SETOGT)>;
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 3225 case ISD::SETOGT: in getVectorComparison() 3345 SDValue LT = getVectorCmp(DAG, getVectorComparison(ISD::SETOGT, Mode), in lowerVectorSETCC() 3362 SDValue LT = getVectorCmp(DAG, getVectorComparison(ISD::SETOGT, Mode), in lowerVectorSETCC() 3364 SDValue GT = getVectorCmp(DAG, getVectorComparison(ISD::SETOGT, Mode), in lowerVectorSETCC()
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/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 2590 ISD::SETOGT); in LowerFROUND32() 2633 ISD::SETOGT); in LowerFROUND64()
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H A D | NVPTXISelDAGToDAG.cpp | 582 case ISD::SETOGT: in getPTXCmpMode()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64SVEInstrInfo.td | 2043 defm FCMGT_PPzZZ : sve_fp_3op_p_pd_cc<0b001, "fcmgt", SETOGT, SETGT, SETOLT, SETLT>; 2051 defm FCMGT_PPzZ0 : sve_fp_2op_p_pd<0b001, "fcmgt", SETOGT, SETGT, SETOLT, SETLT>; 2052 defm FCMLT_PPzZ0 : sve_fp_2op_p_pd<0b010, "fcmlt", SETOLT, SETLT, SETOGT, SETGT>;
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/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
H A D | M68kISelLowering.cpp | 1809 case ISD::SETOGT: in TranslateM68kCC()
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