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Searched refs:SETOGE (Results 1 – 25 of 36) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfoF2.td379 defm : BRCond_Bin_F2<SETOGE, "f2FCMPHS", BT32, BF32, MVC32>;
396 def : Pat<(brcond (i32 (setcc FPR32Op:$rs1, fpimm0, SETOGE)), bb:$imm16),
398 def : Pat<(i32 (setcc FPR32Op:$rs1, fpimm0, SETOGE)),
400 def : Pat<(select (i32 (setcc FPR32Op:$rs1, fpimm0, SETOGE)), FPR32Op:$rx, FPR32Op:$false),
H A DCSKYInstrInfoF1.td359 defm : BRCond_Bin<SETOGE, "FCMPHS", BT32, BF32, MVC32>;
376 def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETOGE)), bb:$imm16),
378 def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETOGE)),
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DAnalysis.cpp204 case FCmpInst::FCMP_OGE: return ISD::SETOGE; in getFCmpCondCode()
228 case ISD::SETOGE: case ISD::SETUGE: return ISD::SETGE; in getFCmpCodeWithoutNaN()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1690 SETOGE, // 0 0 1 1 True if ordered and greater than or equal enumerator
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.h119 case ISD::SETOGE: in fpCondCode2Fcc()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrFloat.td90 defm GE : ComparisonFP<SETOGE, "ge ", 0x60, 0x66>;
H A DWebAssemblyInstrSIMD.td805 defm GE : SIMDConditionFP<"ge", SETOGE, 70>;
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchFloat64InstrInfo.td170 // SETOGT/SETOGE/SETUGT/SETUGE/SETGE/SETNE/SETGT will expand into
H A DLoongArchFloat32InstrInfo.td194 // SETOGT/SETOGE/SETUGT/SETUGE/SETGE/SETNE/SETGT will expand into
H A DLoongArchISelLowering.cpp179 ISD::SETOGT, ISD::SETOGE, ISD::SETUGT, ISD::SETUGE, in LoongArchTargetLowering()
327 setCondCodeAction({ISD::SETGE, ISD::SETGT, ISD::SETOGE, ISD::SETOGT, in LoongArchTargetLowering()
394 setCondCodeAction({ISD::SETGE, ISD::SETGT, ISD::SETOGE, ISD::SETOGT, in LoongArchTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp525 case ISD::SETOGE: return "setoge"; in getOperationName()
H A DTargetLowering.cpp346 case ISD::SETOGE: in softenSetCCOperands()
5450 case ISD::SETOEQ: NewCond = IsNegInf ? ISD::SETOLE : ISD::SETOGE; break; in SimplifySetCC()
8987 ISD::CondCode UnorderedOp = IsInvertedFP ? ISD::SETOGE : ISD::SETULT; in expandIS_FPCLASS()
12200 case ISD::SETOGE: in LegalizeSetCCCondCode()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp4226 case ISD::SETOGE: in SelectCC()
4253 case ISD::SETOGE: in SelectCC()
4291 case ISD::SETOGE: in getPredicateForSetCC()
4342 case ISD::SETOGE: in getCRIdxForSetCC()
4366 case ISD::SETOLE: CC = ISD::SETOGE; Swap = true; break; in getVCmpInst()
4377 case ISD::SETULT: CC = ISD::SETOGE; Negate = true; break; in getVCmpInst()
4397 case ISD::SETOGE: in getVCmpInst()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructions.td351 def COND_OGE : PatFrags<(ops), [(OtherVT SETOGE), (OtherVT SETGE)]>;
H A DSIWholeQuadMode.cpp857 case ISD::SETOGE: in lowerKillF32()
H A DAMDGPUISelLowering.cpp1704 case ISD::SETOGE: in combineFMinMaxLegacyImpl()
2050 SDValue cv = DAG.getSetCC(DL, SetCCVT, fr, fb, ISD::SETOGE); in LowerDIVREM24()
2575 SDValue Cmp = DAG.getSetCC(SL, SetCCVT, AbsDiff, Half, ISD::SETOGE); in LowerFROUND()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp299 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand); in MipsSETargetLowering()
304 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand); in MipsSETargetLowering()
436 setCondCodeAction(ISD::SETOGE, Ty, Expand); in addMSAFloatType()
H A DMipsMSAInstrInfo.td128 def vfsetoge_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGE>;
129 def vfsetoge_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGE>;
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp843 case ISD::SETOGE: in IntCondCCodeToICC()
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td910 def SETOGE : CondCode<"FCMP_OGE">;
1576 (setcc node:$lhs, node:$rhs, SETOGE)>;
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaISelLowering.cpp876 case ISD::SETOGE: in getFPBranchKind()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.cpp378 case ISD::SETOGE: in getPTXCmpMode()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp352 setCondCodeAction(ISD::SETOGE, MVT::v64f16, Expand); in initializeHVXLowering()
367 setCondCodeAction(ISD::SETOGE, MVT::v32f32, Expand); in initializeHVXLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp1815 case ISD::SETOGE: in TranslateM68kCC()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SVEInstrInfo.td2179 defm FCMGE_PPzZZ : sve_fp_3op_p_pd_cc<0b000, "fcmge", SETOGE, SETGE, SETOLE, SETLE>;
2187 defm FCMGE_PPzZ0 : sve_fp_2op_p_pd<0b000, "fcmge", SETOGE, SETGE, SETOLE, SETLE>;
2190 defm FCMLE_PPzZ0 : sve_fp_2op_p_pd<0b011, "fcmle", SETOLE, SETLE, SETOGE, SETGE>;

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