| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsTargetTransformInfo.cpp | 15 return TLI->isOperationLegalOrCustom(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, in hasDivRemOp()
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| H A D | MipsSEISelLowering.cpp | 190 setOperationAction(ISD::SDIVREM, MVT::i64, Custom); in MipsSETargetLowering()
197 setOperationAction(ISD::SDIVREM, MVT::i32, Custom); in MipsSETargetLowering()
235 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); in MipsSETargetLowering()
282 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); in MipsSETargetLowering()
458 case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG); in LowerOperation()
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| H A D | MipsISelLowering.cpp | 517 setTargetDAGCombine({ISD::SDIVREM, ISD::UDIVREM, ISD::SELECT, ISD::AND, in MipsTargetLowering()
585 unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 : in performDivRemCombine()
1176 case ISD::SDIVREM: in PerformDAGCombine()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 262 SDIVREM, enumerator
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| H A D | SelectionDAG.h | 2389 case ISD::SDIVREM:
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| H A D | BasicTTIImpl.h | 938 if (TLI->isOperationLegalOrCustom(IsSigned ? ISD::SDIVREM : ISD::UDIVREM,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 164 setOperationAction(ISD::SDIVREM, MVT::i8, Custom); in AVRTargetLowering()
165 setOperationAction(ISD::SDIVREM, MVT::i16, Custom); in AVRTargetLowering()
166 setOperationAction(ISD::SDIVREM, MVT::i32, Custom); in AVRTargetLowering()
541 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) && in LowerDivRem()
543 bool IsSigned = (Opcode == ISD::SDIVREM); in LowerDivRem()
1000 case ISD::SDIVREM: in LowerOperation()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.h | 95 SDIVREM, enumerator
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| H A D | SystemZOperators.td | 289 def z_sdivrem : SDNode<"SystemZISD::SDIVREM", SDT_ZGR128Binary>;
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| H A D | SystemZISelLowering.cpp | 185 setOperationAction(ISD::SDIVREM, VT, Custom); in SystemZTargetLowering()
243 setOperationAction(ISD::SDIVREM, MVT::i128, Expand); in SystemZTargetLowering()
4197 lowerGR128Binary(DAG, DL, VT, SystemZISD::SDIVREM, Op0, Op1, Ops[1], Ops[0]); in lowerSDIVREM()
6158 case ISD::SDIVREM: in LowerOperation()
6396 OPCODE(SDIVREM); in getTargetNodeName()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 136 setOperationAction(ISD::SDIVREM, MVT::i8, Promote); in MSP430TargetLowering()
142 setOperationAction(ISD::SDIVREM, MVT::i16, Expand); in MSP430TargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 273 case ISD::SDIVREM: return "sdivrem"; in getOperationName()
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| H A D | LegalizeIntegerTypes.cpp | 4558 if (TLI.getOperationAction(ISD::SDIVREM, VT) == TargetLowering::Custom) { in ExpandIntRes_SDIV()
4559 SDValue Res = DAG.getNode(ISD::SDIVREM, dl, DAG.getVTList(VT, VT), Ops); in ExpandIntRes_SDIV()
4872 if (TLI.getOperationAction(ISD::SDIVREM, VT) == TargetLowering::Custom) { in ExpandIntRes_SREM()
4873 SDValue Res = DAG.getNode(ISD::SDIVREM, dl, DAG.getVTList(VT, VT), Ops); in ExpandIntRes_SREM()
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| H A D | LegalizeVectorOps.cpp | 352 case ISD::SDIVREM: in LegalizeOp()
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| H A D | LegalizeDAG.cpp | 2252 bool isSigned = Opcode == ISD::SDIVREM; in ExpandDivRemLibCall()
3779 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; in ExpandNode()
4972 case ISD::SDIVREM: in ConvertNodeToLibcall()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFISelLowering.cpp | 100 setOperationAction(ISD::SDIVREM, VT, Expand); in BPFTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelLowering.cpp | 61 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); in CSKYTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrFragments.td | 683 return (N->getOperand(0).getOpcode() == ISD::SDIVREM &&
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.cpp | 108 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); in LanaiTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 216 setOperationAction(ISD::SDIVREM, VT, Expand); in addTypeForNEON()
299 setOperationAction(ISD::SDIVREM, VT, Expand); in addMVEVectorTypes()
1295 setOperationAction(ISD::SDIVREM, MVT::i32, Custom); in ARMTargetLowering()
1297 setOperationAction(ISD::SDIVREM, MVT::i64, Custom); in ARMTargetLowering()
1300 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); in ARMTargetLowering()
10678 case ISD::SDIVREM: in LowerOperation()
10747 case ISD::SDIVREM: in ReplaceNodeResults()
20679 assert((N->getOpcode() == ISD::SDIVREM || N->getOpcode() == ISD::UDIVREM || in getDivRemLibcall()
20682 bool isSigned = N->getOpcode() == ISD::SDIVREM || in getDivRemLibcall()
20697 assert((N->getOpcode() == ISD::SDIVREM || N->getOpcode() == ISD::UDIVREM || in getDivRemArgList()
[all …]
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| H A D | ARMTargetTransformInfo.cpp | 2106 case ISD::SDIVREM: in maybeLoweredToCall()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 467 setOperationAction({ISD::SDIVREM, ISD::UDIVREM}, VT, Custom); in AMDGPUTargetLowering()
516 ISD::UMUL_LOHI, ISD::SDIVREM, ISD::UDIVREM, in AMDGPUTargetLowering()
1380 case ISD::SDIVREM: return LowerSDIVREM(Op, DAG); in LowerOperation()
2313 SDValue DIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(HalfVT, HalfVT), in LowerSDIVREM()
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| H A D | R600ISelLowering.cpp | 606 case ISD::SDIVREM: { in ReplaceNodeResults()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1675 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); in SparcTargetLowering()
1682 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); in SparcTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1601 ISD::SDIVREM, ISD::UDIVREM, ISD::ROTL, ISD::ROTR, in HexagonTargetLowering()
1647 ISD::SREM, ISD::UREM, ISD::SDIVREM, ISD::UDIVREM, ISD::SADDO, in HexagonTargetLowering()
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