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Searched refs:SCD (Results 1 – 9 of 9) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMLatencyMutations.cpp719 unsigned computeBypassStage(const MCSchedClassDesc *SCD);
722 const MCSchedClassDesc *SCD);
752 const MCSchedClassDesc *SCD) { in modifyMixedWidthFP() argument
765 return 5 - computeBypassStage(SCD); in modifyMixedWidthFP()
771 return 5 - computeBypassStage(SCD) - in modifyMixedWidthFP()
787 return 5 - computeBypassStage(SCD); in modifyMixedWidthFP()
793 return 5 - computeBypassStage(SCD) + in modifyMixedWidthFP()
820 return 5 - computeBypassStage(SCD); in modifyMixedWidthFP()
829 return 5 - computeBypassStage(SCD) - in modifyMixedWidthFP()
842 return 5 - computeBypassStage(SCD); in modifyMixedWidthFP()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSERegisterInfo.cpp82 case Mips::SCD: in getLoadStoreOffsetSizeInBits()
H A DMipsExpandPseudo.cpp235 SC = STI->hasMips64r6() ? Mips::SCD_R6 : Mips::SCD; in expandAtomicCmpSwap()
751 SC = STI->hasMips64r6() ? Mips::SCD_R6 : Mips::SCD; in expandAtomicBinOp()
H A DMips32r6InstrFormats.td60 // The spec occasionally names this value LL, LLD, SC, or SCD.
H A DMipsScheduleGeneric.td690 def : InstRW<[GenericWriteStore], (instrs SD, SC64, SCD, SB64, SH64, SW64,
H A DMips64InstrInfo.td251 def SCD : SCBase<"scd", GPR64Opnd>, LW_FM<0x3c>, ISA_MIPS3_NOT_32R6_64R6;
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp1472 Inst.getOpcode() == Mips::SCD) in DecodeMem()
/freebsd/contrib/llvm-project/clang/lib/Sema/
H A DSemaOpenMP.cpp4109 const Decl *SCD = SC.getAssociatedDeclaration(); in VisitMemberExpr() local
4111 SCD = SCD ? SCD->getCanonicalDecl() : nullptr; in VisitMemberExpr()
4112 if (SCD != CCD) in VisitMemberExpr()
/freebsd/contrib/ncurses/misc/
H A Dterminfo.src22633 # SCD scroll down (72 lines) ^[[1s