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Searched refs:Rx (Results 1 – 25 of 49) sorted by relevance

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/freebsd/sys/contrib/device-tree/Bindings/net/can/
H A Dxilinx_can.txt20 - rx-fifo-depth : Can Rx fifo depth (Zynq, Axi CAN, CAN FD in
21 sequential Rx mode).
23 - rx-mailbox-count : Can Rx mailbox buffer count (CAN FD in mailbox Rx
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstr64Bit.td1196 def : InstAlias<"mtxer $Rx", (MTSPR8 1, g8rc:$Rx)>;
1197 def : InstAlias<"mfxer $Rx", (MFSPR8 g8rc:$Rx, 1)>;
1202 def : InstAlias<"mtudscr $Rx", (MTSPR8 3, g8rc:$Rx)>;
1203 def : InstAlias<"mfudscr $Rx", (MFSPR8 g8rc:$Rx, 3)>;
1205 def : InstAlias<"mfrtcu $Rx", (MFSPR8 g8rc:$Rx, 4)>;
1206 def : InstAlias<"mfrtcl $Rx", (MFSPR8 g8rc:$Rx, 5)>;
1208 def : InstAlias<"mtlr $Rx", (MTSPR8 8, g8rc:$Rx)>;
1209 def : InstAlias<"mflr $Rx", (MFSPR8 g8rc:$Rx, 8)>;
1211 def : InstAlias<"mtctr $Rx", (MTSPR8 9, g8rc:$Rx)>;
1212 def : InstAlias<"mfctr $Rx", (MFSPR8 g8rc:$Rx, 9)>;
[all …]
H A DPPCInstrInfo.td2745 def : InstAlias<"mtudscr $Rx", (MTUDSCR gprc:$Rx)>;
2746 def : InstAlias<"mfudscr $Rx", (MFUDSCR gprc:$Rx)>;
4542 def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>;
4543 def : InstAlias<"mftbl $Rx", (MFTB gprc:$Rx, 268)>;
4544 def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>;
4548 def : InstAlias<"mtxer $Rx", (MTSPR 1, gprc:$Rx)>;
4549 def : InstAlias<"mfxer $Rx", (MFSPR gprc:$Rx, 1)>;
4555 def : InstAlias<"mfbr"#BR#" $Rx",
4556 (MFDCR gprc:$Rx, !add(BR, 0x80))>,
4558 def : InstAlias<"mtbr"#BR#" $Rx",
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6qdl-dhcom-drc02.dtsi14 * pins SD3_DAT0 and SD3_DAT1 are muxed as can2 Tx and Rx. The signals for can2
15 * Tx and Rx are routed to the DHCOM UART1 rts/cts pins. Therefore the micro SD
72 * Due to the use of can2 the signals for can2 Tx and Rx are routed to
110 * can2 Tx and Rx.
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Daltera_tse.txt14 "rx_csr" : xDMA Rx dispatcher control and status space region
15 "rx_desc": MSGDMA Rx dispatcher descriptor space region
16 "rx_resp": MSGDMA Rx dispatcher response space region
20 "rx_irq": xDMA Rx dispatcher interrupt
H A Dsff,sfp.txt28 - rate-select0-gpios : GPIO phandle and a specifier of the Rx Signaling Rate
29 Select (AKA RS0) output gpio signal, low: low Rx rate, high: high Rx rate
H A Damd-xgbe.txt8 - SerDes Rx/Tx registers
18 correct Rx interrupt watchdog timer value on a DMA channel
28 - amd,per-channel-interrupt: Indicates that Rx and Tx complete will generate
H A Dbroadcom-bcm87xx.txt25 * GPIO[1] Tx/Rx
H A Dibm,emac.txt32 - rx-fifo-size : 1 cell, Rx fifo size in bytes for 10 and 100 Mb/sec
76 - rx-fifo-size-gige : 1 cell, Rx fifo size in bytes for 1000 Mb/sec
184 - num-rx-chans : 1 cell, number of Rx channels
H A Dkeystone-netcp.txt142 queue (FDQ) for the pktdma Rx flow. There can be at
143 present a maximum of 4 queues per Rx flow.
144 - rx-buffer-size: the buffer size for each of the Rx flow FDQ.
H A Dapm-xgene-enet.txt18 - First is the Rx interrupt. This irq is mandatory.
H A Dfsl-tsec-phy.txt66 Rx int line. This is an advanced power management capability allowing
/freebsd/sys/contrib/device-tree/Bindings/serial/
H A Dmtk-uart.txt33 index 1: optional, an interrupt specifier with edge sensitivity on Rx pin to
34 support Rx in-band wake up. If one would like to use this feature,
35 one must create an addtional pinctrl to reconfigure Rx pin to normal
H A Dnvidia,tegra20-hsuart.txt39 Tegra186 chip has a known hardware issue. UART Rx baud rate tolerance level
/freebsd/sys/contrib/device-tree/Bindings/soc/ti/
H A Dkeystone-navigator-dma.txt47 - Rx DMA channel configuration register region (rxchan).
49 - Rx DMA flow configuration register region (rxflow).
57 - ti,loop-back: To loopback Tx streaming I/F to Rx streaming I/F. Used for
/freebsd/sys/contrib/device-tree/src/arm/ti/keystone/
H A Dkeystone-k2g-netcp.dtsi83 <0x4012000 0x400>, /* 32 Rx channels */
85 <0x4013000 0x400>; /* 32 Rx flows */
/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dfsl-sai.txt45 with Rx) which means both the transmitter and the
75 default synchronous mode (sync Rx with Tx) will be used, which means both
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/
H A DHexagonAsmParser.cpp1388 MCOperand &Rx = Inst.getOperand(0); in processInstruction() local
1390 if (Rx.getReg() != Hexagon::R0 || Ry.getReg() != Hexagon::R0) { in processInstruction()
1683 MCOperand &Rx = Inst.getOperand(0); in processInstruction() local
1692 TmpInst.addOperand(Rx); in processInstruction()
1693 TmpInst.addOperand(Rx); in processInstruction()
1703 MCOperand &Rx = Inst.getOperand(0); in processInstruction() local
1712 TmpInst.addOperand(Rx); in processInstruction()
1713 TmpInst.addOperand(Rx); in processInstruction()
1723 MCOperand &Rx = Inst.getOperand(0); in processInstruction() local
1732 TmpInst.addOperand(Rx); in processInstruction()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mailbox/
H A Dsti-mailbox.txt20 - interrupts : Contains the IRQ line for a Rx mailbox
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonPatterns.td46 // 5. Compound instructions (e.g. Rx+Rs*Rt) are generated under the condition
337 : Pat<(AccOp RegPred:$Rx, (Op RegPred:$Rs, ImmPred:$I)),
338 (MI RegPred:$Rx, RegPred:$Rs, imm:$I)>;
342 : Pat<(AccOp RxPred:$Rx, (Op RsPred:$Rs, RtPred:$Rt)),
343 (MI RxPred:$Rx, RsPred:$Rs, RtPred:$Rt)>;
1724 def: Pat<(or I32:$Ru, (Su<And> I32:$Rx, anyimm:$s10)),
1725 (S4_or_andix IntRegs:$Ru, IntRegs:$Rx, imm:$s10)>;
1727 def: Pat<(or I32:$Rx, (Su<And> I32:$Rs, anyimm:$s10)),
1728 (S4_or_andi IntRegs:$Rx, IntRegs:$Rs, imm:$s10)>;
1729 def: Pat<(or I32:$Rx, (Su<Or> I32:$Rs, anyimm:$s10)),
[all …]
/freebsd/usr.sbin/chown/tests/
H A Dchown_test.sh191 atf_check chown -Rx 42:42 .
/freebsd/sys/contrib/device-tree/src/arm/marvell/
H A Dorion5x-netgear-wnr854t.dts250 /* Pin 1: Tx, Pin 7: Rx, Pin 8: Gnd */
/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dcnxt,cx92755-pinctrl.txt85 "client select" for the Rx and Tx signals of uart0. The uart0 node references
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dst,stm32-rcc.txt93 17 CLK_SPDIF (SPDIF-Rx clock)
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dti-phy.txt10 "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control

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