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Searched refs:Rt2 (Results 1 – 14 of 14) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp983 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); in DecodeExclusiveLdStInstruction() local
1043 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rt2, Addr, in DecodeExclusiveLdStInstruction()
1055 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt2, Addr, in DecodeExclusiveLdStInstruction()
1066 Rt == Rt2) in DecodeExclusiveLdStInstruction()
1077 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); in DecodePairLdStInstruction() local
1143 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt2, Addr, in DecodePairLdStInstruction()
1158 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rt2, Addr, in DecodePairLdStInstruction()
1171 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(Inst, Rt2, Addr, in DecodePairLdStInstruction()
1184 DecodeSimpleRegisterClass<AArch64::FPR64RegClassID, 0, 32>(Inst, Rt2, Addr, in DecodePairLdStInstruction()
1197 DecodeSimpleRegisterClass<AArch64::FPR32RegClassID, 0, 32>(Inst, Rt2, Addr, in DecodePairLdStInstruction()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp2219 unsigned Rt2 = Rt + 1; in DecodeAddrMode3Instruction() local
2243 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) in DecodeAddrMode3Instruction()
2247 if (Rt2 == 15) in DecodeAddrMode3Instruction()
2266 if (Rt2 == 15) in DecodeAddrMode3Instruction()
2272 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) in DecodeAddrMode3Instruction()
2276 if (writeback && (Rn == Rt || Rn == Rt2)) in DecodeAddrMode3Instruction()
5799 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); in DecodeVMOVSRR() local
5804 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) in DecodeVMOVSRR()
5813 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) in DecodeVMOVSRR()
5825 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); in DecodeVMOVRRS() local
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrVFP.td1230 (outs GPR:$Rt, GPR:$Rt2), (ins DPR:$Dm),
1231 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $Dm",
1232 [(set GPR:$Rt, GPR:$Rt2, (arm_fmrrd DPR:$Dm))]>,
1238 bits<4> Rt2;
1244 let Inst{19-16} = Rt2;
1254 // $Rt2 = EXTRACT_SUBREG $Dm, ssub_1
1259 (outs GPR:$Rt, GPR:$Rt2), (ins SPR:$src1, SPR:$src2),
1260 IIC_fpMOVDI, "vmov", "\t$Rt, $Rt2, $src1, $src2",
1266 bits<4> Rt2;
1272 let Inst{19-16} = Rt2;
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H A DARMInstrThumb2.td1475 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1477 IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", "",
1478 [(set rGPR:$Rt, rGPR:$Rt2, (ARMldrd t2addrmode_imm8s4:$addr))]>,
1706 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4:$addr),
1707 IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", "",
1708 [(ARMstrd rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4:$addr)]>,
1854 def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1856 "ldrd", "\t$Rt, $Rt2, $addr!", "$addr.base = $wb", []>,
1862 def t2LDRD_POST : T2Ii8s4post<0, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1864 IIC_iLoad_d_ru, "ldrd", "\t$Rt, $Rt2, $addr$imm",
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H A DARMInstrInfo.td2873 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode3:$addr),
2874 LdMiscFrm, IIC_iLoad_d_r, "ldrd", "\t$Rt, $Rt2, $addr", []>,
2997 def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
3000 "ldrd", "\t$Rt, $Rt2, $addr!",
3010 def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
3013 "ldrd", "\t$Rt, $Rt2, $addr, $offset",
3157 def STRD : AI3str<0b1111, (outs), (ins GPR:$Rt, GPR:$Rt2, addrmode3:$addr),
3158 StMiscFrm, IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", []>,
3331 (ins GPR:$Rt, GPR:$Rt2, addrmode3_pre:$addr),
3333 "strd", "\t$Rt, $Rt2, $addr!",
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H A DARMInstrFormats.td728 : AI<oops, iops, MiscFrm, NoItinerary, opc, "\t$Rt, $Rt2, $addr", pattern> {
730 bits<4> Rt2;
738 let Inst{3-0} = Rt2;
1427 bits<4> Rt2;
1437 let Inst{11-8} = Rt2{3-0};
1446 bits<4> Rt2;
1457 let Inst{11-8} = Rt2{3-0};
H A DARMInstrMVE.td5873 bits<5> Rt2;
5882 let Inst{19-16} = Rt2{3-0};
5920 (ins MQPR:$QdSrc, rGPR:$Rt, rGPR:$Rt2),
5921 0b1, "$Qd$idx, $QdSrc$idx2, $Rt, $Rt2",
5926 def MVE_VMOV_rr_q : MVE_VMOV_64bit<(outs rGPR:$Rt, rGPR:$Rt2), (ins MQPR:$Qd),
5927 0b0, "$Rt, $Rt2, $Qd$idx, $Qd$idx2", ""> {
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrFormats.td4503 : I<oops, iops, asm, "\t$Rt, $Rt2, [$Rn, $offset]", "", []> {
4505 bits<5> Rt2;
4514 let Inst{14-10} = Rt2;
4525 (outs regtype:$Rt, regtype:$Rt2),
4529 def : InstAlias<asm # "\t$Rt, $Rt2, [$Rn]",
4530 (!cast<Instruction>(NAME # "i") regtype:$Rt, regtype:$Rt2,
4539 (ins regtype:$Rt, regtype:$Rt2,
4544 def : InstAlias<asm # "\t$Rt, $Rt2, [$Rn]",
4545 (!cast<Instruction>(NAME # "i") regtype:$Rt, regtype:$Rt2,
4552 : I<oops, iops, asm, "\t$Rt, $Rt2, [$Rn, $offset]!", "$Rn = $wback,@earlyclobber $wback", []> {
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H A DAArch64InstrInfo.td2673 def : Pat<(int_aarch64_stgp (am_indexed7s128 GPR64sp:$Rn, simm7s16:$imm), GPR64:$Rt, GPR64:$Rt2),
2674 (STGPi $Rt, $Rt2, $Rn, $imm)>;
4052 def : Pat<(AArch64stp GPR64z:$Rt, GPR64z:$Rt2, (am_indexed7s64 GPR64sp:$Rn, simm7s8:$offset)),
4053 (STPXi GPR64z:$Rt, GPR64z:$Rt2, GPR64sp:$Rn, simm7s8:$offset)>;
4055 def : Pat<(AArch64stnp FPR128:$Rt, FPR128:$Rt2, (am_indexed7s128 GPR64sp:$Rn, simm7s16:$offset)),
4056 (STNPQi FPR128:$Rt, FPR128:$Rt2, GPR64sp:$Rn, simm7s16:$offset)>;
10004 …, 0b0000, (outs GPR64sp:$wback), (ins GPR32:$Rt, GPR32:$Rt2, GPR64sp:$Rn), "stilp", "\t$Rt, $Rt2, …
10005 …, 0b0000, (outs GPR64sp:$wback), (ins GPR64:$Rt, GPR64:$Rt2, GPR64sp:$Rn), "stilp", "\t$Rt, $Rt2, …
10006 …Pair<0b10, 0b00, 0b0001, (outs), (ins GPR32:$Rt, GPR32:$Rt2, GPR64sp:$Rn), "stilp", "\t$Rt, $Rt2, …
10007 …Pair<0b11, 0b00, 0b0001, (outs), (ins GPR64:$Rt, GPR64:$Rt2, GPR64sp:$Rn), "stilp", "\t$Rt, $Rt2, …
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/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM64/
H A DEmulateInstructionARM64.cpp701 uint32_t Rt2 = Bits32(opcode, 14, 10); in EmulateLDPSTP() local
707 integer t2 = UInt(Rt2); in EmulateLDPSTP()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp5355 unsigned Rt2 = Inst.getOperand(2).getReg(); in validateInstruction() local
5360 if (RI->isSubRegisterEq(Rn, Rt2)) in validateInstruction()
5380 unsigned Rt2 = Inst.getOperand(1).getReg(); in validateInstruction() local
5381 if (Rt == Rt2) in validateInstruction()
5393 unsigned Rt2 = Inst.getOperand(2).getReg(); in validateInstruction() local
5394 if (Rt == Rt2) in validateInstruction()
5409 unsigned Rt2 = Inst.getOperand(2).getReg(); in validateInstruction() local
5414 if (RI->isSubRegisterEq(Rn, Rt2)) in validateInstruction()
5490 unsigned Rt2 = Inst.getOperand(2).getReg(); in validateInstruction() local
5492 if (RI->isSubRegisterEq(Rt1, Rs) || RI->isSubRegisterEq(Rt2, Rs) || in validateInstruction()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp7415 unsigned Rt2 = MRI->getEncodingValue(Reg2); in ParseInstruction() local
7417 if (Rt + 1 != Rt2) in ParseInstruction()
7554 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(RtIndex + 1).getReg()); in validateLDRDSTRD() local
7568 if (Rt2 != Rt + 1) { in validateLDRDSTRD()
7582 if (Rt2 == Rt) in validateLDRDSTRD()
7590 if (Rn == Rt || Rn == Rt2) { in validateLDRDSTRD()
/freebsd/contrib/llvm-project/clang/lib/CodeGen/
H A DCGBuiltin.cpp8470 Value *Rt2 = Builder.CreateLShr(Call, 32); in EmitAMDGCNBallotForExec() local
8471 Rt2 = Builder.CreateTrunc(Rt2, CGF.Int32Ty); in EmitAMDGCNBallotForExec()
8472 return Rt2; in EmitAMDGCNBallotForExec()
8702 Value *Rt2 = Builder.CreateLShr(RtAndRt2, C1); in EmitARMBuiltinExpr() local
8703 Rt2 = Builder.CreateTruncOrBitCast(Rt2, Int32Ty); in EmitARMBuiltinExpr()
8705 return Builder.CreateCall(F, {Coproc, Opc1, Rt, Rt2, CRm}); in EmitARMBuiltinExpr()
/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM/
H A DEmulateInstructionARM.cpp11162 uint32_t Rt2 = ReadCoreReg(t2, &success); in EmulateSTRDReg() local
11171 if (!MemAWrite(context, address + 4, Rt2, addr_byte_size)) in EmulateSTRDReg()