Lines Matching refs:Rt2
1475 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2),
1477 IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", "",
1478 [(set rGPR:$Rt, rGPR:$Rt2, (ARMldrd t2addrmode_imm8s4:$addr))]>,
1706 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4:$addr),
1707 IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", "",
1708 [(ARMstrd rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4:$addr)]>,
1854 def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1856 "ldrd", "\t$Rt, $Rt2, $addr!", "$addr.base = $wb", []>,
1862 def t2LDRD_POST : T2Ii8s4post<0, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
1864 IIC_iLoad_d_ru, "ldrd", "\t$Rt, $Rt2, $addr$imm",
1869 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4_pre:$addr),
1870 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr!",
1877 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr,
1879 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr$imm",
3709 def t2LDREXD : T2I_ldrex<0b0111, (outs rGPR:$Rt, rGPR:$Rt2),
3712 "ldrexd", "\t$Rt, $Rt2, $addr", "",
3715 bits<4> Rt2;
3716 let Inst{11-8} = Rt2;
3743 def t2LDAEXD : T2I_ldrex<0b1111, (outs rGPR:$Rt, rGPR:$Rt2),
3746 "ldaexd", "\t$Rt, $Rt2, $addr", "",
3749 bits<4> Rt2;
3750 let Inst{11-8} = Rt2;
3791 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr),
3793 "strexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
3796 bits<4> Rt2;
3797 let Inst{11-8} = Rt2;
3837 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr),
3839 "stlexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
3842 bits<4> Rt2;
3843 let Inst{11-8} = Rt2;
4630 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4636 bits<4> Rt2;
4642 let Inst{19-16} = Rt2;
4698 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2,
4700 [(int_arm_mcrr timm:$cop, timm:$opc1, GPR:$Rt, GPR:$Rt2,
4703 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2,
4706 GPR:$Rt2, timm:$CRm)]> {
4711 def t2MRRC : t2MovRRCopro<0b1110, "mrrc", 1, (outs GPR:$Rt, GPR:$Rt2),
4714 def t2MRRC2 : t2MovRRCopro<0b1111, "mrrc2", 1, (outs GPR:$Rt, GPR:$Rt2),