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/freebsd/contrib/llvm-project/clang/lib/Headers/
H A Dhvx_hexagon_protos.h63 #define Q6_V_vsplat_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lvsplatw)(Rt) argument
129 …fine Q6_Q_vsetq_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(_… argument
151 …m_QnRIV(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nqpred_ai)(__BUILTIN_VECTOR_WRA… argument
162 …RIV_nt(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nt_nqpred_ai)(__BUILTIN_VECTOR_W… argument
173 …RIV_nt(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nt_qpred_ai)(__BUILTIN_VECTOR_WR… argument
184 …mem_QRIV(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_qpred_ai)(__BUILTIN_VECTOR_WRA… argument
536 #define Q6_V_valign_VVR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_valignb)(Vu,Vv,Rt) argument
569 … Q6_V_vand_QR(Qu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)(__BUILTIN_VECTOR_WRAP(__b… argument
580 …or_VQR(Vx,Qu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt_acc)(Vx,__BUILTIN_VECTOR_WRAP(… argument
591 …ne Q6_Q_vand_VR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(… argument
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonIntrinsics.td16 : Pat <(IntID I32:$Rs, I32:$Rt),
17 (MI I32:$Rs, I32:$Rt)>;
20 : Pat <(IntID I32:$Rs, I64:$Rt),
21 (MI I32:$Rs, I64:$Rt)>;
23 def: Pat<(int_hexagon_A2_add IntRegs:$Rs, IntRegs:$Rt),
24 (A2_add IntRegs:$Rs, IntRegs:$Rt)>;
27 def: Pat<(int_hexagon_A2_addp DoubleRegs:$Rs, DoubleRegs:$Rt),
28 (A2_addp DoubleRegs:$Rs, DoubleRegs:$Rt)>;
30 def: Pat<(int_hexagon_A2_sub IntRegs:$Rs, IntRegs:$Rt),
31 (A2_sub IntRegs:$Rs, IntRegs:$Rt)>;
[all …]
H A DHexagonPatterns.td46 // 5. Compound instructions (e.g. Rx+Rs*Rt) are generated under the condition
253 def Combinew: OutPatFrag<(ops node:$Rs, node:$Rt),
254 (REG_SEQUENCE DoubleRegs, $Rs, isub_hi, $Rt, isub_lo)>;
332 : Pat<(ResType (Op RsPred:$Rs, RtPred:$Rt)),
333 (MI RsPred:$Rs, RtPred:$Rt)>;
342 : Pat<(AccOp RxPred:$Rx, (Op RsPred:$Rs, RtPred:$Rt)),
343 (MI RxPred:$Rx, RsPred:$Rs, RtPred:$Rt)>;
753 : Pat<(ResType (Op RsPred:$Rs, RtPred:$Rt)),
754 (Output RsPred:$Rs, RtPred:$Rt)>;
757 : OutPatFrag<(ops node:$Rs, node:$Rt),
[all …]
H A DHexagonPatternsHVX.td135 def: Pat<(ResType (Load (add I32:$Rt, ImmPred:$Off))),
136 (MI I32:$Rt, imm:$Off)>;
137 def: Pat<(ResType (Load I32:$Rt)),
138 (MI I32:$Rt, 0)>;
162 def: Pat<(ResType (Load (valignaddr I32:$Rt))),
163 (MI I32:$Rt, 0)>;
164 def: Pat<(ResType (Load (add (valignaddr I32:$Rt), ImmPred:$Off))),
165 (MI I32:$Rt, imm:$Off)>;
207 def: Pat<(Store Value:$Vs, (add I32:$Rt, ImmPred:$Off)),
208 (MI I32:$Rt, imm:$Off, Value:$Vs)>;
[all …]
H A DHexagonPatternsV65.td14 IntRegs:$Rt, ModRegs:$Mu, RC:$Vv),
24 IntRegs:$Rt, ModRegs:$Mu, RC:$Vv),
34 IntRegs:$Rt, ModRegs:$Mu, RC:$Vv),
48 RC2:$Vq, IntRegs:$Rt, ModRegs:$Mu,
59 RC2:$Vq, IntRegs:$Rt, ModRegs:$Mu,
70 RC2:$Vq, IntRegs:$Rt, ModRegs:$Mu,
H A DHexagonIntrinsicsV5.td41 // Rdd=vmpyhsu(Rs,Rt)[:<<1]:sat
45 // Rxx+=vmpyhsu(Rs,Rt)[:<<1]:sat
50 // Rdd=vpmpyh(Rs,Rt)
52 // Rxx[^]=vpmpyh(Rs,Rt)
56 // Rdd=pmpyw(Rs,Rt)
58 // Rxx^=pmpyw(Rs,Rt)
61 //Rxx^=asr(Rss,Rt)
63 //Rxx^=asl(Rss,Rt)
65 //Rxx^=lsr(Rss,Rt)
67 //Rxx^=lsl(Rss,Rt)
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H A DHexagonAsmPrinter.cpp377 MCOperand &Rt = Inst.getOperand(3); in HexagonProcessInstruction() local
378 assert(Rt.isReg() && "Expected register and none was found"); in HexagonProcessInstruction()
379 unsigned Reg = RI->getEncodingValue(Rt.getReg()); in HexagonProcessInstruction()
384 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); in HexagonProcessInstruction()
388 MCOperand &Rt = Inst.getOperand(2); in HexagonProcessInstruction() local
389 assert(Rt.isReg() && "Expected register and none was found"); in HexagonProcessInstruction()
390 unsigned Reg = RI->getEncodingValue(Rt.getReg()); in HexagonProcessInstruction()
395 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); in HexagonProcessInstruction()
400 MCOperand &Rt = Inst.getOperand(2); in HexagonProcessInstruction() local
401 assert(Rt.isReg() && "Expected register and none was found"); in HexagonProcessInstruction()
[all …]
H A DHexagonBitTracker.cpp294 auto shuffle = [this] (const BT::RegisterCell &Rs, const BT::RegisterCell &Rt, in evaluate()
297 assert(Ws == Rt.width()); in evaluate()
298 RegisterCell RC = eXTR(Rt, I*BW, I*BW+BW).cat(eXTR(Rs, I*BW, I*BW+BW)); in evaluate()
301 RC.cat(eXTR(Rt, I*BW, I*BW+BW)).cat(eXTR(Rs, I*BW, I*BW+BW)); in evaluate()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrThumb2.td1196 def i12 : T2Ii12<(outs target:$Rt), (ins t2addrmode_imm12:$addr), iii,
1197 opc, ".w\t$Rt, $addr",
1198 [(set target:$Rt, (opnode t2addrmode_imm12:$addr))]>,
1200 bits<4> Rt;
1208 let Inst{15-12} = Rt;
1213 def i8 : T2Ii8n <(outs target:$Rt), (ins t2addrmode_negimm8:$addr), iii,
1214 opc, "\t$Rt, $addr",
1215 [(set target:$Rt, (opnode t2addrmode_negimm8:$addr))]>,
1217 bits<4> Rt;
1226 let Inst{15-12} = Rt;
[all …]
H A DARMInstrInfo.td2028 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
2029 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
2030 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
2031 bits<4> Rt;
2035 let Inst{15-12} = Rt;
2038 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
2039 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
2040 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
2041 bits<4> Rt;
2046 let Inst{15-12} = Rt;
[all …]
H A DARMInstrVFP.td1180 (outs GPR:$Rt), (ins SPR:$Sn),
1181 IIC_fpMOVSI, "vmov", "\t$Rt, $Sn",
1182 [(set GPR:$Rt, (bitconvert SPR:$Sn))]>,
1186 bits<4> Rt;
1192 let Inst{15-12} = Rt;
1204 (outs SPR:$Sn), (ins GPR:$Rt),
1205 IIC_fpMOVIS, "vmov", "\t$Sn, $Rt",
1206 [(set SPR:$Sn, (bitconvert GPR:$Rt))]>,
1211 bits<4> Rt;
1216 let Inst{15-12} = Rt;
[all …]
H A DARMInstrThumb.td692 def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
693 "ldr", "\t$Rt, $addr",
694 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>,
697 bits<3> Rt;
699 let Inst{10-8} = Rt;
706 def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
707 "ldr", "\t$Rt, $addr",
708 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>,
710 bits<3> Rt;
712 let Inst{10-8} = Rt;
[all …]
H A DARMInstrFormats.td674 bits<4> Rt;
680 let Inst{15-12} = Rt;
689 bits<4> Rt;
698 let Inst{3-0} = Rt;
728 : AI<oops, iops, MiscFrm, NoItinerary, opc, "\t$Rt, $Rt2, $addr", pattern> {
729 bits<4> Rt;
736 let Inst{15-12} = Rt;
800 bits<4> Rt;
806 let Inst{15-12} = Rt;
868 bits<4> Rt;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp618 InsnType Rt = fieldFromInstruction(insn, 16, 5); in DecodeAddiGroupBranch() local
622 if (Rs >= Rt) { in DecodeAddiGroupBranch()
625 } else if (Rs != 0 && Rs < Rt) { in DecodeAddiGroupBranch()
636 Rt))); in DecodeAddiGroupBranch()
646 InsnType Rt = fieldFromInstruction(insn, 21, 5); in DecodePOP35GroupBranchMMR6() local
650 if (Rs >= Rt) { in DecodePOP35GroupBranchMMR6()
653 Rt))); in DecodePOP35GroupBranchMMR6()
657 } else if (Rs != 0 && Rs < Rt) { in DecodePOP35GroupBranchMMR6()
662 Rt))); in DecodePOP35GroupBranchMMR6()
667 Rt))); in DecodePOP35GroupBranchMMR6()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp707 unsigned Rt = fieldFromInstruction(insn, 0, 5); in DecodeUnsignedLdStInstruction() local
716 Inst.addOperand(MCOperand::createImm(Rt)); in DecodeUnsignedLdStInstruction()
726 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rt, Addr, in DecodeUnsignedLdStInstruction()
734 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt, Addr, in DecodeUnsignedLdStInstruction()
739 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(Inst, Rt, Addr, in DecodeUnsignedLdStInstruction()
744 DecodeSimpleRegisterClass<AArch64::FPR64RegClassID, 0, 32>(Inst, Rt, Addr, in DecodeUnsignedLdStInstruction()
749 DecodeSimpleRegisterClass<AArch64::FPR32RegClassID, 0, 32>(Inst, Rt, Addr, in DecodeUnsignedLdStInstruction()
754 DecodeSimpleRegisterClass<AArch64::FPR16RegClassID, 0, 32>(Inst, Rt, Addr, in DecodeUnsignedLdStInstruction()
759 DecodeSimpleRegisterClass<AArch64::FPR8RegClassID, 0, 32>(Inst, Rt, Addr, in DecodeUnsignedLdStInstruction()
774 unsigned Rt = fieldFromInstruction(insn, 0, 5); in DecodeSignedLdStInstruction() local
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCCompound.cpp201 MCOperand Rs, Rt; in getCompoundInsn() local
211 Rt = L.getOperand(0); in getCompoundInsn()
216 CompoundInsn->addOperand(Rt); in getCompoundInsn()
222 Rt = L.getOperand(0); in getCompoundInsn()
228 CompoundInsn->addOperand(Rt); in getCompoundInsn()
237 Rt = L.getOperand(2); in getCompoundInsn()
243 CompoundInsn->addOperand(Rt); in getCompoundInsn()
250 Rt = L.getOperand(2); in getCompoundInsn()
256 CompoundInsn->addOperand(Rt); in getCompoundInsn()
263 Rt = L.getOperand(2); in getCompoundInsn()
[all …]
/freebsd/contrib/llvm-project/compiler-rt/lib/xray/
H A Dxray_mips.cpp41 uint32_t Rt, in encodeInstruction() argument
43 return (Opcode | Rs << 21 | Rt << 16 | Imm); in encodeInstruction()
47 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd, in encodeSpecialInstruction() argument
49 return (Rs << 21 | Rt << 16 | Rd << 11 | Imm << 6 | Opcode); in encodeSpecialInstruction()
H A Dxray_mips64.cpp42 uint32_t Rt, in encodeInstruction() argument
44 return (Opcode | Rs << 21 | Rt << 16 | Imm); in encodeInstruction()
48 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd, in encodeSpecialInstruction() argument
50 return (Rs << 21 | Rt << 16 | Rd << 11 | Imm << 6 | Opcode); in encodeSpecialInstruction()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.td1293 : RtSystemI<0, (outs), (ins GPR64:$Rt), mnemonic, "\t$Rt", pattern> {
1309 : RtSystemI<1, (outs GPR64:$Rt), (ins GPR64:$src), mnemonic, "\t$Rt", pattern> {
1318 let Constraints = "$src = $Rt";
1326 [(set GPR64:$Rt, (int_aarch64_gcspopm GPR64:$src))]>;
1327 def GCSPOPM_NoOp : InstAlias<"gcspopm", (GCSPOPM XZR)>, Requires<[HasGCS]>; // Rt defaults to XZR i…
1342 : I<(outs), (ins GPR64:$Rt, GPR64sp:$Rn), mnemonic, "\t$Rt, [$Rn]", "", []>, Sched<[]> {
1343 bits<5> Rt;
1349 let Inst{4-0} = Rt;
2095 [(set GPR64:$Rt, (int_aarch64_tstart))]>;
2102 def TTEST : TMSystemI<0b0001, "ttest", [(set GPR64:$Rt, (int_aarch64_ttest))]> {
[all …]
H A DAArch64InstrFormats.td1655 // System instructions which do not have an Rt register.
1662 // System instructions which have an Rt register.
1667 bits<5> Rt;
1668 let Inst{4-0} = Rt;
1688 (outs GPR64:$Rt), (ins), asm, "\t$Rt", pattern> {
1689 bits<5> Rt;
1690 let Inst{4-0} = Rt;
1697 : RtSystemI<0, (outs), (ins GPR64:$Rt), asm, "\t$Rt", pattern> {
1828 class MRSI : RtSystemI<1, (outs GPR64:$Rt), (ins mrs_sysreg_op:$systemreg),
1829 "mrs", "\t$Rt, $systemreg"> {
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp2048 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeAddrMode2IdxInstruction() local
2073 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) in DecodeAddrMode2IdxInstruction()
2107 if (writeback && (Rn == 15 || Rn == Rt)) in DecodeAddrMode2IdxInstruction()
2210 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeAddrMode3Instruction() local
2219 unsigned Rt2 = Rt + 1; in DecodeAddrMode3Instruction()
2231 if (Rt & 0x1) S = MCDisassembler::SoftFail; in DecodeAddrMode3Instruction()
2243 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) in DecodeAddrMode3Instruction()
2255 if (Rt == 15) in DecodeAddrMode3Instruction()
2257 if (writeback && (Rn == 15 || Rn == Rt)) in DecodeAddrMode3Instruction()
2272 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) in DecodeAddrMode3Instruction()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/
H A DHexagonAsmParser.cpp1445 MCOperand &Rt = Inst.getOperand(1); in processInstruction() local
1448 TmpInst.addOperand(Rt); in processInstruction()
1449 TmpInst.addOperand(Rt); in processInstruction()
1866 MCOperand &Rt = Inst.getOperand(2); in processInstruction() local
1867 unsigned int RegNum = RI->getEncodingValue(Rt.getReg()); in processInstruction()
1872 Rt.setReg(matchRegister(RegPair)); in processInstruction()
1877 Rt.setReg(matchRegister(RegPair)); in processInstruction()
1886 MCOperand &Rt = Inst.getOperand(3); in processInstruction() local
1887 unsigned int RegNum = RI->getEncodingValue(Rt.getReg()); in processInstruction()
1892 Rt.setReg(matchRegister(RegPair)); in processInstruction()
[all …]
/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM/
H A DEmulateInstructionARM.cpp927 uint32_t Rt; // the source register in EmulatePUSH() local
946 Rt = Bits32(opcode, 15, 12); in EmulatePUSH()
948 if (BadReg(Rt)) in EmulatePUSH()
950 registers = (1u << Rt); in EmulatePUSH()
959 Rt = Bits32(opcode, 15, 12); in EmulatePUSH()
961 if (Rt == dwarf_sp) in EmulatePUSH()
963 registers = (1u << Rt); in EmulatePUSH()
1043 uint32_t Rt; // the destination register in EmulatePOP() local
1067 Rt = Bits32(opcode, 15, 12); in EmulatePOP()
1070 if (Rt == 13) in EmulatePOP()
[all …]
/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM64/
H A DEmulateInstructionARM64.cpp703 uint32_t Rt = Bits32(opcode, 4, 0); in EmulateLDPSTP() local
706 integer t = UInt(Rt); in EmulateLDPSTP()
1131 integer t = UInt(Rt); in EmulateCBZ()
1169 integer t = UInt(Rt); in EmulateTBZ()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVMergeBaseOffset.cpp187 Register Rt = TailAdd.getOperand(2).getReg(); in foldLargeOffset() local
188 Register Reg = Rs == GAReg ? Rt : Rs; in foldLargeOffset()

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