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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.td808 def AArch64fcvtxnsdr: PatFrags<(ops node:$Rn),
809 [(f32 (int_aarch64_sisd_fcvtxn (f64 node:$Rn))),
810 (f32 (AArch64fcvtxn_n (f64 node:$Rn)))]>;
811 def AArch64fcvtxnv: PatFrags<(ops node:$Rn),
812 [(int_aarch64_neon_fcvtxn node:$Rn),
813 (AArch64fcvtxn_n node:$Rn)]>;
876 def AArch64addp : PatFrags<(ops node:$Rn, node:$Rm),
877 [(AArch64addp_n node:$Rn, node:$Rm),
878 (int_aarch64_neon_addp node:$Rn, node:$Rm)]>;
885 def AArch64faddp : PatFrags<(ops node:$Rn, node:$Rm),
[all …]
H A DAArch64InstrAtomics.td66 def : Pat<(relaxed_load<atomic_load_az_8> (ro_Windexed8 GPR64sp:$Rn, GPR32:$Rm,
68 (LDRBBroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend8:$offset)>;
69 def : Pat<(relaxed_load<atomic_load_az_8> (ro_Xindexed8 GPR64sp:$Rn, GPR64:$Rm,
71 (LDRBBroX GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$offset)>;
72 def : Pat<(relaxed_load<atomic_load_az_8> (am_indexed8 GPR64sp:$Rn,
74 (LDRBBui GPR64sp:$Rn, uimm12s1:$offset)>;
76 (am_unscaled8 GPR64sp:$Rn, simm9:$offset)),
77 (LDURBBi GPR64sp:$Rn, simm9:$offset)>;
82 def : Pat<(relaxed_load<atomic_load_az_16> (ro_Windexed16 GPR64sp:$Rn, GPR32:$Rm,
84 (LDRHHroW GPR64sp:$Rn, GPR32:$Rm, ro_Wextend16:$extend)>;
[all …]
H A DAArch64InstrGISel.td323 def : Pat<(f32 (fadd (vector_extract (v2f32 FPR64:$Rn), (i64 0)),
324 (vector_extract (v2f32 FPR64:$Rn), (i64 1)))),
325 (f32 (FADDPv2i32p (v2f32 FPR64:$Rn)))>;
371 def : PatIgnoreCopies<(i32 (sext (i8 (intOp (v8i8 V64:$Rn))))),
374 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
376 def : Pat<(i8 (intOp (v8i8 V64:$Rn))),
377 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn)>;
379 def : PatIgnoreCopies<(i32 (sext (i8 (intOp (v16i8 V128:$Rn))))),
382 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
384 def : Pat<(i8 (intOp (v16i8 V128:$Rn))),
[all …]
H A DAArch64InstrFormats.td1998 : BaseBranchReg<opc, (outs), (ins GPR64:$Rn), asm, "\t$Rn", pattern> {
1999 bits<5> Rn;
2000 let Inst{9-5} = Rn;
2011 : I<(outs RC:$Rt), (ins GPR64sp0:$Rn), asm, "\t$Rt, [$Rn]", "", []>,
2013 bits<5> Rn;
2017 let Inst{9-5} = Rn;
2032 : AuthBase<M, (outs), (ins GPR64:$Rn, GPR64sp:$Rm), asm, "\t$Rn, $Rm", []> {
2033 bits<5> Rn;
2037 let Inst{9-5} = Rn;
2042 : AuthBase<M, (outs), (ins GPR64:$Rn), asm, "\t$Rn", []> {
[all …]
H A DSVEInstrFormats.td578 : Pat<(vt (op pt:$Pg, vt:$Rn, (vt (splat_vector (it (cast i32:$imm)))))),
579 (inst $Pg, $Rn, i32:$imm)>;
584 : Pat<(vt (op (pt (SVEAnyPredicate)), vt:$Rn, (vt (splat_vector (it (cast i32:$imm)))))),
585 (inst $Rn, i32:$imm)>;
876 def : Pat<(i32 (op GPR32:$Rn, (nxv16i1 PPRAny:$Pg))),
877 … (!cast<Instruction>(NAME # _B) PPRAny:$Pg, (INSERT_SUBREG (IMPLICIT_DEF), $Rn, sub_32)), sub_32)>;
878 def : Pat<(i64 (sext (i32 (op GPR32:$Rn, (nxv16i1 PPRAny:$Pg))))),
879 … (!cast<Instruction>(NAME # _B) PPRAny:$Pg, (INSERT_SUBREG (IMPLICIT_DEF), $Rn, sub_32))>;
881 def : Pat<(i32 (op GPR32:$Rn, (nxv8i1 PPRAny:$Pg))),
882 … (!cast<Instruction>(NAME # _H) PPRAny:$Pg, (INSERT_SUBREG (IMPLICIT_DEF), $Rn, sub_32)), sub_32)>;
[all …]
H A DSMEInstrFormats.td509 bits<5> Rn;
518 let Inst{9-5} = Rn;
529 (ins MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm, PPR3bAny:$Pg, GPR64sp:$Rn,
531 mnemonic, "\t\\{$ZAt[$Rv, $imm]\\}, $Pg/z, [$Rn, $Rm]">;
537 def : InstAlias<mnemonic # "\t$ZAt[$Rv, $imm], $Pg" # pg_suffix # ", [$Rn, $Rm]",
538 …tile_ty:$ZAt, MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, gpr_ty:$Rm), 0>;
540 def : InstAlias<mnemonic # "\t\\{$ZAt[$Rv, $imm]\\}, $Pg" # pg_suffix # ", [$Rn]",
541 … (inst tile_ty:$ZAt, MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR), 1>;
542 def : InstAlias<mnemonic # "\t$ZAt[$Rv, $imm], $Pg" # pg_suffix # ", [$Rn]",
543 … (inst tile_ty:$ZAt, MatrixIndexGPR32Op12_15:$Rv, imm_ty:$imm, PPR3bAny:$Pg, GPR64sp:$Rn, XZR), 0>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrThumb2.td359 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
365 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
459 bits<4> Rn;
471 bits<4> Rn;
474 let Inst{19-16} = Rn;
510 bits<4> Rn;
513 let Inst{19-16} = Rn;
543 bits<4> Rn;
546 let Inst{19-16} = Rn;
555 bits<4> Rn;
[all …]
H A DARMInstrInfo.td1549 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1556 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1557 iii, opc, "\t$Rd, $Rn, $imm",
1558 [(set GPR:$Rd, (opnode GPR:$Rn, mod_imm:$imm))]>,
1561 bits<4> Rn;
1564 let Inst{19-16} = Rn;
1569 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1570 iir, opc, "\t$Rd, $Rn, $Rm",
1571 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1574 bits<4> Rn;
[all …]
H A DARMInstrThumb.td423 def tADDspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
434 def tSUBspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
455 def tADDrSP : T1pI<(outs GPR:$Rdn), (ins GPRsp:$sp, GPR:$Rn), IIC_iALUr,
456 "add", "\t$Rdn, $sp, $Rn", []>,
467 def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr,
826 def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
827 IIC_iLoad_m, "ldm${p}\t$Rn, $regs", []>, T1Encoding<{1,1,0,0,1,?}> {
828 bits<3> Rn;
830 let Inst{10-8} = Rn;
840 "$Rn = $wb", IIC_iLoad_mu>,
[all …]
H A DARMInstrNEON.td544 : PseudoVFPLdStM<(outs DPair:$dst), (ins GPR:$Rn),
546 [(set DPair:$dst, (v2f64 (word_alignedload GPR:$Rn)))]>;
551 : PseudoVFPLdStM<(outs), (ins DPair:$src, GPR:$Rn),
553 [(word_alignedstore (v2f64 DPair:$src), GPR:$Rn)]>;
601 (ins AddrMode:$Rn), IIC_VLD1,
602 "vld1", Dt, "$Vd, $Rn", "", []>, Sched<[WriteVLD1]> {
604 let Inst{4} = Rn{4};
609 (ins AddrMode:$Rn), IIC_VLD1x2,
610 "vld1", Dt, "$Vd, $Rn", "", []>, Sched<[WriteVLD2]> {
612 let Inst{5-4} = Rn{5-4};
[all …]
H A DARMInstrCDE.td84 dag Rn;
132 !strconcat(iname, params.PAsm, "\t$coproc, $Rd, $Rn, $imm"),
136 bits<4> Rn;
140 let Inst{19-16} = Rn{3-0};
150 !strconcat(iname, params.PAsm, "\t$coproc, $Rd, $Rn, $Rm, $imm"),
154 bits<4> Rn;
159 let Inst{19-16} = Rn{3-0};
170 let Rn = (ins GPRwithAPSR_NZCVnosp:$Rn);
178 let Rn = (ins GPRwithAPSR_NZCVnosp:$Rn);
189 let Iops2 = !con(IOpsPrefix, ops.Rn);
[all …]
H A DARMSchedule.td17 // Rd <- ADD Rn, Rm, <shift> Rs
19 // 2 | Rn: 1 Rm: 4 Rs: 4 | uop T0, Rm, Rs - P01 - 3
20 // | | uopc Rd, Rn, T0 - P01 - 1
23 // and one cycle after the result in Rn is available. The micro-ops can execute
26 // that the resource P01 is needed and that the latency to Rn is different than
27 // the latency to Rm and Rs. The scheduler can decrease Rn's producer latency by
H A DARMInstrFormats.td75 // The instruction has an Rn register operand.
77 // it doesn't have a Rn operand.
817 bits<4> Rn;
820 let Inst{19-16} = Rn;
835 bits<4> Rn;
838 let Inst{19-16} = Rn;
851 // {17-14} Rn
875 let Inst{19-16} = addr{12-9}; // Rn
905 // {12-9} Rn
915 let Inst{19-16} = addr; // Rn
[all …]
H A DARMInstrVFP.td231 AXDI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
233 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
239 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
242 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
248 AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs,
251 !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
259 AXSI4<(outs), (ins GPR:$Rn, pred:$p, spr_reglist:$regs, variable_ops),
261 !strconcat(asm, "ia${p}\t$Rn, $regs"), "", []> {
271 AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, spr_reglist:$regs,
274 !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
[all …]
H A DARMInstrMVE.td354 def : Pat<(VTI.Vec (Op (VTI.Vec MQPR:$Qm), (VTI.Vec (ARMvdup rGPR:$Rn)))),
355 (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), rGPR:$Rn))>;
361 (VTI.Vec (ARMvdup rGPR:$Rn)))),
363 (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), rGPR:$Rn,
370 (ARMvdup rGPR:$Rn),
372 (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), rGPR:$Rn,
378 def : Pat<(VTI.Vec !con((PredInt (VTI.Vec MQPR:$Qm), (VTI.Vec (ARMvdup rGPR:$Rn))),
381 (VTI.Vec (Inst (VTI.Vec MQPR:$Qm), rGPR:$Rn,
5382 def : Pat<(VTI.Vec (shift_op (add_op (VTI.Vec MQPR:$Qm), (VTI.Vec (ARMvdup rGPR:$Rn))), (i32 1))),
5383 (Inst MQPR:$Qm, rGPR:$Rn)>;
[all...]
H A DThumb2SizeReduction.cpp466 Register Rn = MI->getOperand(IsStore ? 0 : 1).getReg(); in ReduceLoadStore() local
471 assert(isARMLowRegister(Rn)); in ReduceLoadStore()
479 .addReg(Rn, RegState::Define) in ReduceLoadStore()
480 .addReg(Rn) in ReduceLoadStore()
/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM/
H A DEmulateInstructionARM.cpp2480 Rn; // This function assumes Rn is the SP, but we should verify that. in EmulateSTRRtSP() local
2489 Rn = Bits32(opcode, 19, 16); in EmulateSTRRtSP()
2491 if (Rn != 13) // 13 is the SP reg on ARM. Verify that Rn == SP. in EmulateSTRRtSP()
2498 if (wback && ((Rn == 15) || (Rn == Rt))) in EmulateSTRRtSP()
2951 uint32_t Rn; // the base register which contains the address of the table of in EmulateTB() local
2958 Rn = Bits32(opcode, 19, 16); in EmulateTB()
2961 if (Rn == 13 || BadReg(Rm)) in EmulateTB()
2972 uint32_t base = ReadCoreReg(Rn, &success); in EmulateTB()
3101 uint64_t Rn = in EmulateADDImmThumb() local
3107 AddWithCarryResult res = AddWithCarry(Rn, imm32, 0); in EmulateADDImmThumb()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp502 unsigned Rn = fieldFromInstruction(Insn, 5, 5); in DecodeFMOVLaneInstruction() local
509 Inst, Rn, Address, Decoder); in DecodeFMOVLaneInstruction()
514 Inst, Rn, Address, Decoder); in DecodeFMOVLaneInstruction()
605 unsigned Rn = fieldFromInstruction(insn, 5, 5); in DecodeThreeAddrSRegInstruction() local
634 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rn, Addr, in DecodeThreeAddrSRegInstruction()
658 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rn, Addr, in DecodeThreeAddrSRegInstruction()
708 unsigned Rn = fieldFromInstruction(insn, 5, 5); in DecodeUnsignedLdStInstruction() local
764 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr, in DecodeUnsignedLdStInstruction()
775 unsigned Rn = fieldFromInstruction(insn, 5, 5); in DecodeSignedLdStInstruction() local
833 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr, in DecodeSignedLdStInstruction()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1872 unsigned Rn = fieldFromInstruction(Insn, 16, 4); in DecodeCopMemInstruction() local
1951 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) in DecodeCopMemInstruction()
2047 unsigned Rn = fieldFromInstruction(Insn, 16, 4); in DecodeAddrMode2IdxInstruction() local
2066 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) in DecodeAddrMode2IdxInstruction()
2086 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) in DecodeAddrMode2IdxInstruction()
2093 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) in DecodeAddrMode2IdxInstruction()
2107 if (writeback && (Rn == 15 || Rn == Rt)) in DecodeAddrMode2IdxInstruction()
2153 unsigned Rn = fieldFromInstruction(Val, 13, 4); in DecodeSORegMemOperand() local
2178 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) in DecodeSORegMemOperand()
2211 unsigned Rn = fieldFromInstruction(Insn, 16, 4); in DecodeAddrMode3Instruction() local
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfoF1.td223 def : Pat<(i32 (fp_to_sint (round sFPR32Op:$Rn))),
224 (COPY_TO_REGCLASS (!cast<Instruction>(SUFFIX # FSTOSI) sFPR32Op:$Rn), GPR)>,
226 def : Pat<(i32 (fp_to_uint (round sFPR32Op:$Rn))),
227 (COPY_TO_REGCLASS (!cast<Instruction>(SUFFIX # FSTOUI) sFPR32Op:$Rn), GPR)>,
229 def : Pat<(i32 (fp_to_sint (round sFPR64Op:$Rn))),
230 (COPY_TO_REGCLASS (!cast<Instruction>(SUFFIX # FDTOSI) sFPR64Op:$Rn), GPR)>,
232 def : Pat<(i32 (fp_to_uint (round sFPR64Op:$Rn))),
233 (COPY_TO_REGCLASS (!cast<Instruction>(SUFFIX # FDTOUI) sFPR64Op:$Rn), GPR)>,
242 def : Pat<(i32 (fp_to_sint sFPR32Op:$Rn)),
243 (COPY_TO_REGCLASS (!cast<Instruction>(SUFFIX # FSTOSI) sFPR32Op:$Rn), GP
[all...]
/freebsd/sys/arm64/arm64/
H A Dundefined.c206 int attempts, error, Rn, Rd, Rm; in swp_emulate() local
223 Rn = (insn & 0xf0000) >> 16; in swp_emulate()
228 vaddr = regs[Rn] & 0xffffffff; in swp_emulate()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCCodeEmitter.cpp917 // [Rn, Rm] in getThumbAdrLabelOpValue()
919 // {2-0} = Rn in getThumbAdrLabelOpValue()
922 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
924 return (Rm << 3) | Rn;
987 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. in getAddrModeImm12OpValue()
1053 // {6-3} Rn in getT2ScaledImmOpValue()
1058 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(M0.getReg());
1063 return (Rn << 3) | Qm; in getMveAddrModeRQOpValue()
1112 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. in getT2AddrModeImm8s4OpValue()
1276 unsigned Rn in getHiLoImmOpValue()
933 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); getThumbAddrModeRegRegOpValue() local
1069 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(M0.getReg()); getMveAddrModeRQOpValue() local
1287 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); getLdStSORegOpValue() local
1384 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. getAddrMode3OpValue() local
1394 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); getAddrMode3OpValue() local
1431 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); getAddrModeISOpValue() local
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kSchedule.td17 let LoadLatency = 4; // Word (Rn)
/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM64/
H A DEmulateInstructionARM64.cpp621 const uint32_t Rn = Bits32(opcode, 9, 5); in EmulateADDSUBImm() local
627 const uint32_t n = UInt(Rn); in EmulateADDSUBImm()
702 uint32_t Rn = Bits32(opcode, 9, 5); in EmulateLDPSTP() local
705 integer n = UInt(Rn); in EmulateLDPSTP()
/freebsd/secure/caroot/trusted/
H A DTelekom_Security_TLS_ECC_Root_2020.pem66 z6fLHgIwN0GMZt9Ba9aDAEH9L1r3ULRn0SyocddDypwnJJGDSA3PzfdUga/sf+Rn

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