Lines Matching refs:Rn
1549 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1556 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1557 iii, opc, "\t$Rd, $Rn, $imm",
1558 [(set GPR:$Rd, (opnode GPR:$Rn, mod_imm:$imm))]>,
1561 bits<4> Rn;
1564 let Inst{19-16} = Rn;
1569 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1570 iir, opc, "\t$Rd, $Rn, $Rm",
1571 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1574 bits<4> Rn;
1578 let Inst{19-16} = Rn;
1585 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1586 iis, opc, "\t$Rd, $Rn, $shift",
1587 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>,
1590 bits<4> Rn;
1593 let Inst{19-16} = Rn;
1601 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1602 iis, opc, "\t$Rd, $Rn, $shift",
1603 [(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>,
1606 bits<4> Rn;
1609 let Inst{19-16} = Rn;
1622 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1629 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1630 iii, opc, "\t$Rd, $Rn, $imm",
1631 [(set GPR:$Rd, (opnode mod_imm:$imm, GPR:$Rn))]>,
1634 bits<4> Rn;
1637 let Inst{19-16} = Rn;
1642 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1643 iir, opc, "\t$Rd, $Rn, $Rm",
1647 bits<4> Rn;
1653 let Inst{19-16} = Rn;
1657 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
1658 iis, opc, "\t$Rd, $Rn, $shift",
1659 [(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>,
1662 bits<4> Rn;
1665 let Inst{19-16} = Rn;
1673 (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
1674 iis, opc, "\t$Rd, $Rn, $shift",
1675 [(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>,
1678 bits<4> Rn;
1681 let Inst{19-16} = Rn;
1699 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p),
1701 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm))]>,
1704 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
1706 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>,
1711 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1713 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1718 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1720 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1731 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p),
1733 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn))]>,
1737 (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
1740 GPR:$Rn))]>,
1744 (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
1747 GPR:$Rn))]>,
1760 def ri : AI1<opcod, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, iii,
1761 opc, "\t$Rn, $imm",
1762 [(opnode GPR:$Rn, mod_imm:$imm)]>,
1764 bits<4> Rn;
1768 let Inst{19-16} = Rn;
1774 def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
1775 opc, "\t$Rn, $Rm",
1776 [(opnode GPR:$Rn, GPR:$Rm)]>,
1778 bits<4> Rn;
1783 let Inst{19-16} = Rn;
1792 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
1793 opc, "\t$Rn, $shift",
1794 [(opnode GPR:$Rn, so_reg_imm:$shift)]>,
1796 bits<4> Rn;
1800 let Inst{19-16} = Rn;
1809 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
1810 opc, "\t$Rn, $shift",
1811 [(opnode GPRnopc:$Rn, so_reg_reg:$shift)]>,
1813 bits<4> Rn;
1817 let Inst{19-16} = Rn;
1860 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1861 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot",
1862 [(set GPRnopc:$Rd, (opnode GPR:$Rn,
1867 bits<4> Rn;
1869 let Inst{19-16} = Rn;
1877 : AExtI<opcod, (outs GPRnopc:$Rd), (ins GPR:$Rn, GPRnopc:$Rm, rot_imm:$rot),
1878 IIC_iEXTAr, opc, "\t$Rd, $Rn, $Rm$rot", []>,
1880 bits<4> Rn;
1882 let Inst{19-16} = Rn;
1887 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1891 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm),
1892 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1893 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm, CPSR))]>,
1897 bits<4> Rn;
1901 let Inst{19-16} = Rn;
1904 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1905 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1906 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1910 bits<4> Rn;
1917 let Inst{19-16} = Rn;
1920 (ins GPR:$Rn, so_reg_imm:$shift),
1921 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1922 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
1926 bits<4> Rn;
1929 let Inst{19-16} = Rn;
1936 (ins GPRnopc:$Rn, so_reg_reg:$shift),
1937 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1939 (opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>,
1943 bits<4> Rn;
1946 let Inst{19-16} = Rn;
1958 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1961 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm),
1962 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1963 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn, CPSR))]>,
1967 bits<4> Rn;
1971 let Inst{19-16} = Rn;
1974 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
1975 DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
1979 bits<4> Rn;
1985 let Inst{19-16} = Rn;
1987 def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
1988 DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
1989 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
1993 bits<4> Rn;
1996 let Inst{19-16} = Rn;
2002 def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
2003 DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
2004 [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
2008 bits<4> Rn;
2011 let Inst{19-16} = Rn;
2034 let Inst{19-16} = addr{16-13}; // Rn
2045 let Inst{19-16} = shift{16-13}; // Rn
2065 let Inst{19-16} = addr{16-13}; // Rn
2077 let Inst{19-16} = shift{16-13}; // Rn
2097 let Inst{19-16} = addr{16-13}; // Rn
2108 let Inst{19-16} = shift{16-13}; // Rn
2126 let Inst{19-16} = addr{16-13}; // Rn
2138 let Inst{19-16} = shift{16-13}; // Rn
2223 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
2224 "\t$Rd, $Rn, $Rm",
2225 [(set GPR:$Rd, (int_arm_sel GPR:$Rn, GPR:$Rm))]>,
2228 bits<4> Rn;
2232 let Inst{19-16} = Rn;
2309 let Inst{19-16} = addr{16-13}; // Rn
2325 let Inst{19-16} = shift{16-13}; // Rn
2765 : XI<(outs), (ins GPR:$Rn), AddrModeNone, 4, IndexModeNone, BrFrm,
2767 bits<4> Rn;
2773 let Inst{19-16} = Rn;
2777 def RFEDA : RFEI<0, "rfeda\t$Rn"> {
2780 def RFEDA_UPD : RFEI<1, "rfeda\t$Rn!"> {
2783 def RFEDB : RFEI<0, "rfedb\t$Rn"> {
2786 def RFEDB_UPD : RFEI<1, "rfedb\t$Rn!"> {
2789 def RFEIA : RFEI<0, "rfeia\t$Rn"> {
2792 def RFEIA_UPD : RFEI<1, "rfeia\t$Rn!"> {
2795 def RFEIB : RFEI<0, "rfeib\t$Rn"> {
2798 def RFEIB_UPD : RFEI<1, "rfeib\t$Rn!"> {
2971 let Inst{19-16} = addr{12-9}; // Rn
3005 let Inst{19-16} = addr{12-9}; // Rn
3183 let Inst{19-16} = addr{16-13}; // Rn
3196 let Inst{19-16} = addr{16-13}; // Rn
3267 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in {
3269 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
3272 (pre_store GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
3274 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
3277 (pre_store GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
3279 (ins GPR:$Rt, GPR:$Rn, am2offset_imm:$offset, pred:$p),
3282 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_imm:$offset))]>;
3284 (ins GPR:$Rt, GPR:$Rn, am2offset_reg:$offset, pred:$p),
3287 (pre_truncsti8 GPR:$Rt, GPR:$Rn, am2offset_reg:$offset))]>;
3289 (ins GPR:$Rt, GPR:$Rn, am3offset:$offset, pred:$p),
3292 (pre_truncsti16 GPR:$Rt, GPR:$Rn, am3offset:$offset))]>;
3305 let Inst{19-16} = addr{12-9}; // Rn
3338 let Inst{19-16} = addr{12-9}; // Rn
3487 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3489 !strconcat(asm, "${p}\t$Rn, $regs", sfx), "", []> {
3496 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3498 !strconcat(asm, "${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3507 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3509 !strconcat(asm, "da${p}\t$Rn, $regs", sfx), "", []> {
3516 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3518 !strconcat(asm, "da${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3527 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3529 !strconcat(asm, "db${p}\t$Rn, $regs", sfx), "", []> {
3536 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3538 !strconcat(asm, "db${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3547 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3549 !strconcat(asm, "ib${p}\t$Rn, $regs", sfx), "", []> {
3556 AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
3558 !strconcat(asm, "ib${p}\t$Rn!, $regs", sfx), "$Rn = $wb", []> {
3585 def LDMIA_RET : ARMPseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
3588 (LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
3589 RegConstraint<"$Rn = $wb">;
3763 def : ARMV6Pat<(add rGPR:$Rn, (sext_inreg (srl rGPR:$Rm, rot_imm:$rot), i8)),
3764 (SXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
3765 def : ARMV6Pat<(add rGPR:$Rn, (sext_inreg (srl rGPR:$Rm, imm8_or_16:$rot),
3767 (SXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
3809 def : ARMV6Pat<(add rGPR:$Rn, (and (srl rGPR:$Rm, rot_imm:$rot), 0xFF)),
3810 (UXTAB rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
3811 def : ARMV6Pat<(add rGPR:$Rn, (and (srl rGPR:$Rm, imm8_or_16:$rot), 0xFFFF)),
3812 (UXTAH rGPR:$Rn, rGPR:$Rm, rot_imm:$rot)>;
3824 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3826 "sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3829 bits<4> Rn;
3837 let Inst{3-0} = Rn;
3841 (ins GPRnopc:$Rn, imm0_31:$lsb, imm1_32:$width),
3843 "ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
3846 bits<4> Rn;
3854 let Inst{3-0} = Rn;
3931 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3932 string asm = "\t$Rd, $Rn, $Rm">
3935 bits<4> Rn;
3940 let Inst{19-16} = Rn;
3952 (ins GPRnopc:$Rm, GPRnopc:$Rn),
3953 "\t$Rd, $Rm, $Rn">;
3958 [(set GPRnopc:$Rd, (intrinsic GPRnopc:$Rn, GPRnopc:$Rm))]>;
3969 (int_arm_qadd GPRnopc:$Rn, GPRnopc:$Rn)))]>;
3972 (int_arm_qadd GPRnopc:$Rn, GPRnopc:$Rn)))]>;
3974 [(set GPRnopc:$Rd, (int_arm_qsub GPRnopc:$Rm, GPRnopc:$Rn))]>;
3977 [(set GPRnopc:$Rd, (int_arm_qadd GPRnopc:$Rm, GPRnopc:$Rn))]>;
3984 def : ARMV5TEPat<(saddsat rGPR:$Rm, (saddsat rGPR:$Rn, rGPR:$Rn)),
3985 (QDADD rGPR:$Rm, rGPR:$Rn)>;
3986 def : ARMV5TEPat<(ssubsat rGPR:$Rm, (saddsat rGPR:$Rn, rGPR:$Rn)),
3987 (QDSUB rGPR:$Rm, rGPR:$Rn)>;
3989 def : ARMV6Pat<(ARMqadd8b rGPR:$Rm, rGPR:$Rn),
3990 (QADD8 rGPR:$Rm, rGPR:$Rn)>;
3991 def : ARMV6Pat<(ARMqsub8b rGPR:$Rm, rGPR:$Rn),
3992 (QSUB8 rGPR:$Rm, rGPR:$Rn)>;
3993 def : ARMV6Pat<(ARMqadd16b rGPR:$Rm, rGPR:$Rn),
3994 (QADD16 rGPR:$Rm, rGPR:$Rn)>;
3995 def : ARMV6Pat<(ARMqsub16b rGPR:$Rm, rGPR:$Rn),
3996 (QSUB16 rGPR:$Rm, rGPR:$Rn)>;
4007 def : ARMV6Pat<(ARMuqadd8b rGPR:$Rm, rGPR:$Rn),
4008 (UQADD8 rGPR:$Rm, rGPR:$Rn)>;
4009 def : ARMV6Pat<(ARMuqsub8b rGPR:$Rm, rGPR:$Rn),
4010 (UQSUB8 rGPR:$Rm, rGPR:$Rn)>;
4011 def : ARMV6Pat<(ARMuqadd16b rGPR:$Rm, rGPR:$Rn),
4012 (UQADD16 rGPR:$Rm, rGPR:$Rn)>;
4013 def : ARMV6Pat<(ARMuqsub16b rGPR:$Rm, rGPR:$Rn),
4014 (UQSUB16 rGPR:$Rm, rGPR:$Rn)>;
4049 def USAD8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4051 "\t$Rd, $Rn, $Rm",
4052 [(set GPR:$Rd, (int_arm_usad8 GPR:$Rn, GPR:$Rm))]>,
4055 bits<4> Rn;
4062 let Inst{3-0} = Rn;
4064 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
4066 "\t$Rd, $Rn, $Rm, $Ra",
4067 [(set GPR:$Rd, (int_arm_usada8 GPR:$Rn, GPR:$Rm, GPR:$Ra))]>,
4070 bits<4> Rn;
4078 let Inst{3-0} = Rn;
4083 (ins imm1_32:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
4084 SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []>,
4088 bits<4> Rn;
4096 let Inst{3-0} = Rn;
4100 (ins imm1_16:$sat_imm, GPRnopc:$Rn), SatFrm,
4101 NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", []>,
4105 bits<4> Rn;
4110 let Inst{3-0} = Rn;
4114 (ins imm0_31:$sat_imm, GPRnopc:$Rn, shift_imm:$sh),
4115 SatFrm, NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []>,
4119 bits<4> Rn;
4127 let Inst{3-0} = Rn;
4131 (ins imm0_15:$sat_imm, GPRnopc:$Rn), SatFrm,
4132 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []>,
4136 bits<4> Rn;
4141 let Inst{3-0} = Rn;
4148 def : ARMPat<(ARMssat GPRnopc:$Rn, imm0_31:$imm),
4149 (SSAT imm0_31:$imm, GPRnopc:$Rn, 0)>;
4150 def : ARMPat<(ARMusat GPRnopc:$Rn, imm0_31:$imm),
4151 (USAT imm0_31:$imm, GPRnopc:$Rn, 0)>;
4164 def : ARMPat<(ARMssat (shl GPRnopc:$Rn, imm0_31:$shft), imm0_31:$pos),
4165 (SSAT imm0_31:$pos, GPRnopc:$Rn, imm0_31:$shft)>;
4166 def : ARMPat<(ARMssat (sra GPRnopc:$Rn, asr_imm:$shft), imm0_31:$pos),
4167 (SSAT imm0_31:$pos, GPRnopc:$Rn, asr_imm:$shft)>;
4168 def : ARMPat<(ARMusat (shl GPRnopc:$Rn, imm0_31:$shft), imm0_31:$pos),
4169 (USAT imm0_31:$pos, GPRnopc:$Rn, imm0_31:$shft)>;
4170 def : ARMPat<(ARMusat (sra GPRnopc:$Rn, asr_imm:$shft), imm0_31:$pos),
4171 (USAT imm0_31:$pos, GPRnopc:$Rn, asr_imm:$shft)>;
4207 def BFI:I<(outs GPRnopc:$Rd), (ins GPRnopc:$src, GPR:$Rn, bf_inv_mask_imm:$imm),
4209 "bfi", "\t$Rd, $Rn, $imm", "$src = $Rd",
4210 [(set GPRnopc:$Rd, (ARMbfi GPRnopc:$src, GPR:$Rn,
4214 bits<4> Rn;
4217 let Inst{6-4} = 0b001; // Rn: Inst{3-0} != 15
4221 let Inst{3-0} = Rn;
4293 bits<4> Rn;
4296 let Inst{3-0} = Rn;
4304 bits<4> Rn;
4308 let Inst{3-0} = Rn;
4316 bits<4> Rn;
4320 let Inst{3-0} = Rn;
4326 let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in {
4328 (ins GPRnopc:$Rn, GPRnopc:$Rm),
4329 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
4330 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
4338 def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
4341 [(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
4342 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
4348 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra),
4349 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
4350 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))]>,
4359 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
4361 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))],
4362 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s)>,
4366 def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
4367 IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
4368 [(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
4373 bits<4> Rn;
4378 let Inst{3-0} = Rn;
4385 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
4386 "smull", "\t$RdLo, $RdHi, $Rn, $Rm",
4388 (smullohi GPR:$Rn, GPR:$Rm))]>,
4393 (ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
4394 "umull", "\t$RdLo, $RdHi, $Rn, $Rm",
4396 (umullohi GPR:$Rn, GPR:$Rm))]>,
4402 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
4405 (smullohi GPR:$Rn, GPR:$Rm))],
4406 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
4411 (ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
4414 (umullohi GPR:$Rn, GPR:$Rm))],
4415 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
4423 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
4424 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4428 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
4429 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4434 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
4436 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4442 bits<4> Rn;
4446 let Inst{3-0} = Rn;
4452 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
4454 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
4459 (ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
4461 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
4470 def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4471 IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
4472 [(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
4478 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4479 IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm",
4480 [(set GPR:$Rd, (ARMsmmlar GPR:$Rn, GPR:$Rm, (i32 0)))]>,
4487 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
4488 IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
4489 [(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
4494 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
4495 IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra",
4496 [(set GPR:$Rd, (ARMsmmlar GPR:$Rn, GPR:$Rm, GPR:$Ra))]>,
4501 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
4502 IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>,
4507 (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
4508 IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra",
4509 [(set GPR:$Rd, (ARMsmmlsr GPR:$Rn, GPR:$Rm, GPR:$Ra))]>,
4514 def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4515 IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
4516 [(set GPR:$Rd, (bb_mul GPR:$Rn, GPR:$Rm))]>,
4520 def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4521 IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
4522 [(set GPR:$Rd, (bt_mul GPR:$Rn, GPR:$Rm))]>,
4526 def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4527 IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
4528 [(set GPR:$Rd, (tb_mul GPR:$Rn, GPR:$Rm))]>,
4532 def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4533 IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
4534 [(set GPR:$Rd, (tt_mul GPR:$Rn, GPR:$Rm))]>,
4538 def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4539 IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
4540 [(set GPR:$Rd, (ARMsmulwb GPR:$Rn, GPR:$Rm))]>,
4544 def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4545 IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
4546 [(set GPR:$Rd, (ARMsmulwt GPR:$Rn, GPR:$Rm))]>,
4555 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4556 IIC_iMAC16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
4558 (bb_mul GPRnopc:$Rn, GPRnopc:$Rm)))]>,
4563 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4564 IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
4566 (bt_mul GPRnopc:$Rn, GPRnopc:$Rm)))]>,
4571 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4572 IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
4574 (tb_mul GPRnopc:$Rn, GPRnopc:$Rm)))]>,
4579 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4580 IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
4582 (tt_mul GPRnopc:$Rn, GPRnopc:$Rm)))]>,
4587 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4588 IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
4590 (add GPR:$Ra, (ARMsmulwb GPRnopc:$Rn, GPRnopc:$Rm)))]>,
4595 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4596 IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
4598 (add GPR:$Ra, (ARMsmulwt GPRnopc:$Rn, GPRnopc:$Rm)))]>,
4611 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi),
4612 IIC_iMAC64, asm, "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4622 def : ARMV5TEPat<(ARMsmlalbb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
4623 (SMLALBB $Rn, $Rm, $RLo, $RHi)>;
4624 def : ARMV5TEPat<(ARMsmlalbt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
4625 (SMLALBT $Rn, $Rm, $RLo, $RHi)>;
4626 def : ARMV5TEPat<(ARMsmlaltb GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
4627 (SMLALTB $Rn, $Rm, $RLo, $RHi)>;
4628 def : ARMV5TEPat<(ARMsmlaltt GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
4629 (SMLALTT $Rn, $Rm, $RLo, $RHi)>;
4636 bits<4> Rn;
4646 let Inst{3-0} = Rn;
4675 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4676 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">,
4680 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4681 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">,
4685 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi),
4687 !strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">,
4692 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi),
4694 !strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">,
4702 def : ARMV6Pat<(int_arm_smlad GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4703 (SMLAD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>;
4704 def : ARMV6Pat<(int_arm_smladx GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4705 (SMLADX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>;
4706 def : ARMV6Pat<(int_arm_smlsd GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4707 (SMLSD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>;
4708 def : ARMV6Pat<(int_arm_smlsdx GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4709 (SMLSDX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra)>;
4710 def : ARMV6Pat<(ARMSmlald GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi),
4711 (SMLALD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>;
4712 def : ARMV6Pat<(ARMSmlaldx GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi),
4713 (SMLALDX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>;
4714 def : ARMV6Pat<(ARMSmlsld GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi),
4715 (SMLSLD GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>;
4716 def : ARMV6Pat<(ARMSmlsldx GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi),
4717 (SMLSLDX GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$RLo, GPRnopc:$RHi)>;
4721 def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
4722 NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">,
4724 def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
4725 NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">,
4732 def : ARMV6Pat<(int_arm_smuad GPRnopc:$Rn, GPRnopc:$Rm),
4733 (SMUAD GPRnopc:$Rn, GPRnopc:$Rm)>;
4734 def : ARMV6Pat<(int_arm_smuadx GPRnopc:$Rn, GPRnopc:$Rm),
4735 (SMUADX GPRnopc:$Rn, GPRnopc:$Rm)>;
4736 def : ARMV6Pat<(int_arm_smusd GPRnopc:$Rn, GPRnopc:$Rm),
4737 (SMUSD GPRnopc:$Rn, GPRnopc:$Rm)>;
4738 def : ARMV6Pat<(int_arm_smusdx GPRnopc:$Rn, GPRnopc:$Rm),
4739 (SMUSDX GPRnopc:$Rn, GPRnopc:$Rm)>;
4744 def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
4745 "sdiv", "\t$Rd, $Rn, $Rm",
4746 [(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>,
4750 def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
4751 "udiv", "\t$Rd, $Rn, $Rm",
4752 [(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>,
4785 def : ARMV6Pat<(truncstorei16 (srl (bswap GPR:$Rn), (i32 16)), addrmode3:$addr),
4786 (STRH (REV16 GPR:$Rn), addrmode3:$addr)>;
4787 def : ARMV6Pat<(srl (bswap top16Zero:$Rn), (i32 16)),
4788 (REV16 GPR:$Rn)>;
4802 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_lsl_amt:$sh),
4803 IIC_iALUsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
4804 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
4811 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
4812 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, 0)>;
4813 def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (shl GPRnopc:$Rm, imm16_31:$sh)),
4814 (PKHBT GPRnopc:$Rn, GPRnopc:$Rm, imm16_31:$sh)>;
4819 (ins GPRnopc:$Rn, GPRnopc:$Rm, pkh_asr_amt:$sh),
4820 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
4821 [(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
4850 : AInoP<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm), MiscFrm, NoItinerary,
4851 !strconcat("crc32", suffix), "\t$Rd, $Rn, $Rm",
4852 [(set GPRnopc:$Rd, (builtin GPRnopc:$Rn, GPRnopc:$Rm))]>,
4855 bits<4> Rn;
4862 let Inst{19-16} = Rn;
4930 def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, IIC_iCMPi,
4931 "cmn", "\t$Rn, $imm",
4932 [(ARMcmn GPR:$Rn, mod_imm:$imm)]>,
4934 bits<4> Rn;
4938 let Inst{19-16} = Rn;
4946 def CMNzrr : AI1<0b1011, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, IIC_iCMPr,
4947 "cmn", "\t$Rn, $Rm",
4949 GPR:$Rn, GPR:$Rm)]>, Sched<[WriteCMP, ReadALU, ReadALU]> {
4950 bits<4> Rn;
4955 let Inst{19-16} = Rn;
4964 (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, IIC_iCMPsr,
4965 "cmn", "\t$Rn, $shift",
4967 GPR:$Rn, so_reg_imm:$shift)]>,
4969 bits<4> Rn;
4973 let Inst{19-16} = Rn;
4983 (ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, IIC_iCMPsr,
4984 "cmn", "\t$Rn, $shift",
4986 GPRnopc:$Rn, so_reg_reg:$shift)]>,
4988 bits<4> Rn;
4992 let Inst{19-16} = Rn;
5834 def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
5835 "msr", "\t$mask, $Rn", []> {
5837 bits<4> Rn;
5845 let Inst{3-0} = Rn;
5864 def MSRbanked : ABI<0b0001, (outs), (ins banked_reg:$banked, GPRnopc:$Rn),
5865 NoItinerary, "msr", "\t$banked, $Rn", []>,
5868 bits<4> Rn;
5878 let Inst{3-0} = Rn;
6164 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0x00FF)),
6165 (UXTAB GPR:$Rn, GPR:$Rm, 0)>;
6166 def : ARMV6Pat<(add GPR:$Rn, (and GPR:$Rm, 0xFFFF)),
6167 (UXTAH GPR:$Rn, GPR:$Rm, 0)>;
6173 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i8)),
6174 (SXTAB GPR:$Rn, GPRnopc:$Rm, 0)>;
6175 def : ARMV6Pat<(add GPR:$Rn, (sext_inreg GPRnopc:$Rm, i16)),
6176 (SXTAH GPR:$Rn, GPRnopc:$Rm, 0)>;
6263 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm",
6264 (PKHBT GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, 0, pred:$p), 0>,
6266 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm",
6267 (PKHBT GPRnopc:$Rd, GPRnopc:$Rm, GPRnopc:$Rn, 0, pred:$p), 0>,
6275 def : ARMInstAlias<"ssat${p} $Rd, $sat_imm, $Rn",
6276 (SSAT GPRnopc:$Rd, imm1_32:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
6277 def : ARMInstAlias<"usat${p} $Rd, $sat_imm, $Rn",
6278 (USAT GPRnopc:$Rd, imm0_31:$sat_imm, GPRnopc:$Rn, 0, pred:$p)>;
6282 def : ARMInstAlias<"sxtab${p} $Rd, $Rn, $Rm",
6283 (SXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
6284 def : ARMInstAlias<"sxtah${p} $Rd, $Rn, $Rm",
6285 (SXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
6286 def : ARMInstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
6287 (SXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
6295 def : ARMInstAlias<"uxtab${p} $Rd, $Rn, $Rm",
6296 (UXTAB GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
6297 def : ARMInstAlias<"uxtah${p} $Rd, $Rn, $Rm",
6298 (UXTAH GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
6299 def : ARMInstAlias<"uxtab16${p} $Rd, $Rn, $Rm",
6300 (UXTAB16 GPRnopc:$Rd, GPR:$Rn, GPRnopc:$Rm, 0, pred:$p)>;
6353 def : ARMInstSubst<"bic${s}${p} $Rd, $Rn, $imm",
6354 (ANDri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm,
6359 def : ARMInstSubst<"and${s}${p} $Rd, $Rn, $imm",
6360 (BICri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm,
6367 def : ARMInstSubst<"add${s}${p} $Rd, $Rn, $imm",
6368 (SUBri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
6372 def : ARMInstSubst<"sub${s}${p} $Rd, $Rn, $imm",
6373 (ADDri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
6378 def : ARMInstSubst<"adc${s}${p} $Rd, $Rn, $imm",
6379 (SBCri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
6382 def : ARMInstSubst<"sbc${s}${p} $Rd, $Rn, $imm",
6383 (ADCri GPR:$Rd, GPR:$Rn, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
6414 let TwoOperandAliasConstraint = "$Rn = $Rd" in {
6415 def ASRr : ARMAsmPseudo<"asr${s}${p} $Rd, $Rn, $Rm",
6416 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
6418 def LSRr : ARMAsmPseudo<"lsr${s}${p} $Rd, $Rn, $Rm",
6419 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
6421 def LSLr : ARMAsmPseudo<"lsl${s}${p} $Rd, $Rn, $Rm",
6422 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
6424 def RORr : ARMAsmPseudo<"ror${s}${p} $Rd, $Rn, $Rm",
6425 (ins GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p,
6440 def : InstAlias<"mul${s}${p} $Rd, $Rn, $Rm",
6441 (MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s), 0>,
6443 def : InstAlias<"mla${s}${p} $Rd, $Rn, $Rm, $Ra",
6444 (MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra,
6447 def : InstAlias<"smlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
6448 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
6450 def : InstAlias<"umlal${s}${p} $RdLo, $RdHi, $Rn, $Rm",
6451 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
6453 def : InstAlias<"smull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
6454 (SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
6456 def : InstAlias<"umull${s}${p} $RdLo, $RdHi, $Rn, $Rm",
6457 (UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
6465 def SPACE : PseudoInst<(outs GPR:$Rd), (ins i32imm:$size, GPR:$Rn),
6467 [(set GPR:$Rd, (int_arm_space timm:$size, GPR:$Rn))]>;