Searched refs:RetReg (Results 1 – 9 of 9) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
| H A D | X86CallLowering.cpp | 152 Register RetReg = STI.is64Bit() ? X86::RAX : X86::EAX; in lowerReturn() local
156 MIRBuilder.buildCopy(RetReg, FLI.DemoteRegister); in lowerReturn()
157 MIB.addReg(RetReg); in lowerReturn()
159 MIRBuilder.buildCopy(RetReg, Reg); in lowerReturn()
160 MIB.addReg(RetReg); in lowerReturn()
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| /freebsd/contrib/llvm-project/clang/lib/StaticAnalyzer/Checkers/ |
| H A D | DynamicTypePropagation.cpp | 305 const MemRegion *RetReg = Call.getReturnValue().getAsRegion(); in checkPostCall() local
306 if (!RetReg) in checkPostCall()
338 C.addTransition(setDynamicTypeInfo(State, RetReg, DynResTy, false)); in checkPostCall()
348 C.addTransition(setDynamicTypeInfo(State, RetReg, RecDynType)); in checkPostCall()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 1710 Register RetReg = VA.getLocReg(); in SelectRet() local
1719 TII.get(TargetOpcode::COPY), RetReg).addReg(SrcReg); in SelectRet()
1721 RetRegs.push_back(RetReg); in SelectRet()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FastISel.cpp | 1293 Register RetReg = Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX; in X86SelectRet() local
1295 TII.get(TargetOpcode::COPY), RetReg).addReg(Reg); in X86SelectRet()
1296 RetRegs.push_back(RetReg); in X86SelectRet()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 2867 Register RetReg = MF.addLiveIn(SP::I7, TLI.getRegClassFor(PtrVT)); in LowerRETURNADDR() local
2868 RetAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, RetReg, VT); in LowerRETURNADDR()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 3942 for (Register RetReg : RetRegs) in selectRet() local
3943 MIB.addReg(RetReg, RegState::Implicit); in selectRet()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsInstrInfo.td | 1594 Register RetReg, RegisterOperand ResRO = RO>:
1596 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)> {
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 4093 SDValue RetReg = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, in ReplaceNodeResults() local
4095 Results.push_back(RetReg); in ReplaceNodeResults()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 14504 SDValue RetReg = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, in ReplaceNodeResults() local
14506 Results.push_back(RetReg); in ReplaceNodeResults()
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