Searched refs:RetReg (Results 1 – 7 of 7) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
| H A D | X86CallLowering.cpp | 153 Register RetReg = STI.is64Bit() ? X86::RAX : X86::EAX; in lowerReturn() local
157 MIRBuilder.buildCopy(RetReg, FLI.DemoteRegister); in lowerReturn()
158 MIB.addReg(RetReg); in lowerReturn()
160 MIRBuilder.buildCopy(RetReg, Reg); in lowerReturn()
161 MIB.addReg(RetReg); in lowerReturn()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 1721 Register RetReg = VA.getLocReg(); in SelectRet() local
1730 TII.get(TargetOpcode::COPY), RetReg).addReg(SrcReg); in SelectRet()
1732 RetRegs.push_back(RetReg); in SelectRet()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FastISel.cpp | 1294 unsigned RetReg = Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX; in X86SelectRet() local
1296 TII.get(TargetOpcode::COPY), RetReg).addReg(Reg); in X86SelectRet()
1297 RetRegs.push_back(RetReg); in X86SelectRet()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 2901 Register RetReg = MF.addLiveIn(SP::I7, TLI.getRegClassFor(PtrVT)); in LowerRETURNADDR() local
2902 RetAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, RetReg, VT); in LowerRETURNADDR()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 3944 for (unsigned RetReg : RetRegs) in selectRet() local
3945 MIB.addReg(RetReg, RegState::Implicit); in selectRet()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsInstrInfo.td | 1582 Register RetReg, RegisterOperand ResRO = RO>:
1584 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)> {
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 6325 SDValue RetReg = in LowerOperation()
6327 return RetReg; in LowerOperation()
12625 SDValue RetReg = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, in ReplaceNodeResults()
12627 Results.push_back(RetReg); in ReplaceNodeResults()
6323 SDValue RetReg = LowerOperation() local
12622 SDValue RetReg = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ReplaceNodeResults() local
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