Searched refs:ResultReg1 (Results 1 – 1 of 1) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 3692 unsigned ResultReg1 = 0, ResultReg2 = 0, MulReg = 0; in fastLowerIntrinsicCall() local
3697 ResultReg1 = emitAdd(VT, LHS, RHS, /*SetFlags=*/true); in fastLowerIntrinsicCall()
3701 ResultReg1 = emitAdd(VT, LHS, RHS, /*SetFlags=*/true); in fastLowerIntrinsicCall()
3705 ResultReg1 = emitSub(VT, LHS, RHS, /*SetFlags=*/true); in fastLowerIntrinsicCall()
3709 ResultReg1 = emitSub(VT, LHS, RHS, /*SetFlags=*/true); in fastLowerIntrinsicCall()
3773 ResultReg1 = createResultReg(TLI.getRegClassFor(VT)); in fastLowerIntrinsicCall()
3775 TII.get(TargetOpcode::COPY), ResultReg1).addReg(MulReg); in fastLowerIntrinsicCall()
3778 if (!ResultReg1) in fastLowerIntrinsicCall()
3785 assert((ResultReg1 + 1) == ResultReg2 && in fastLowerIntrinsicCall()
3787 updateValueMap(II, ResultReg1, 2); in fastLowerIntrinsicCall()
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