3692     unsigned ResultReg1 = 0, ResultReg2 = 0, MulReg = 0;  in fastLowerIntrinsicCall()  local
3697       ResultReg1 = emitAdd(VT, LHS, RHS, /*SetFlags=*/true);  in fastLowerIntrinsicCall()
3701       ResultReg1 = emitAdd(VT, LHS, RHS, /*SetFlags=*/true);  in fastLowerIntrinsicCall()
3705       ResultReg1 = emitSub(VT, LHS, RHS, /*SetFlags=*/true);  in fastLowerIntrinsicCall()
3709       ResultReg1 = emitSub(VT, LHS, RHS, /*SetFlags=*/true);  in fastLowerIntrinsicCall()
3773       ResultReg1 = createResultReg(TLI.getRegClassFor(VT));  in fastLowerIntrinsicCall()
3775               TII.get(TargetOpcode::COPY), ResultReg1).addReg(MulReg);  in fastLowerIntrinsicCall()
3778     if (!ResultReg1)  in fastLowerIntrinsicCall()
3785     assert((ResultReg1 + 1) == ResultReg2 &&  in fastLowerIntrinsicCall()
3787     updateValueMap(II, ResultReg1, 2);  in fastLowerIntrinsicCall()
5080   const Register ResultReg1 = createResultReg(ResRC);  in selectAtomicCmpXchg()  local
5086       .addDef(ResultReg1)  in selectAtomicCmpXchg()
5094       .addUse(ResultReg1)  in selectAtomicCmpXchg()
5104   assert((ResultReg1 + 1) == ResultReg2 && "Nonconsecutive result registers.");  in selectAtomicCmpXchg()
5105   updateValueMap(I, ResultReg1, 2);  in selectAtomicCmpXchg()