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Searched refs:ResNo (Results 1 – 21 of 21) sorted by relevance

/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenDAGPatterns.h467 MVT::SimpleValueType getKnownType(unsigned ResNo) const;
693 ValueTypeByHwMode getType(unsigned ResNo) const { in getType() argument
694 return Types[ResNo].getValueTypeByHwMode(); in getType()
697 const TypeSetByHwMode &getExtType(unsigned ResNo) const { in getExtType() argument
698 return Types[ResNo]; in getExtType()
700 TypeSetByHwMode &getExtType(unsigned ResNo) { return Types[ResNo]; } in getExtType() argument
701 void setType(unsigned ResNo, const TypeSetByHwMode &T) { Types[ResNo] = T; } in setType() argument
702 MVT::SimpleValueType getSimpleType(unsigned ResNo) const { in getSimpleType() argument
703 return Types[ResNo].getMachineValueType().SimpleTy; in getSimpleType()
706 bool hasConcreteType(unsigned ResNo) const { in hasConcreteType() argument
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H A DCodeGenDAGPatterns.cpp1596 unsigned &ResNo) { in getOperandNum() argument
1599 ResNo = OpNo; in getOperandNum()
1626 unsigned ResNo = 0; // The result number being referenced. in ApplyTypeConstraint() local
1627 TreePatternNode &NodeToApply = getOperandNum(OperandNo, N, NodeInfo, ResNo); in ApplyTypeConstraint()
1633 return NodeToApply.UpdateNodeType(ResNo, VVT, TP); in ApplyTypeConstraint()
1636 return NodeToApply.UpdateNodeType(ResNo, MVT::iPTR, TP); in ApplyTypeConstraint()
1639 return TI.EnforceInteger(NodeToApply.getExtType(ResNo)); in ApplyTypeConstraint()
1642 return TI.EnforceFloatingPoint(NodeToApply.getExtType(ResNo)); in ApplyTypeConstraint()
1645 return TI.EnforceVector(NodeToApply.getExtType(ResNo)); in ApplyTypeConstraint()
1650 return (int)NodeToApply.UpdateNodeType(ResNo, OtherNode.getExtType(OResNo), in ApplyTypeConstraint()
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H A DDAGISelMatcher.h521 unsigned ResNo; variable
525 : Matcher(CheckType), Type(type), ResNo(resno) {} in CheckTypeMatcher()
528 unsigned getResNo() const { return ResNo; } in getResNo()
H A DDAGISelMatcher.cpp184 OS.indent(indent) << "CheckType " << getEnumName(Type) << ", ResNo=" << ResNo in printImpl()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSDNodeDbgValue.h50 return u.s.ResNo; in getResNo()
71 static SDDbgOperand fromNode(SDNode *Node, unsigned ResNo) { in fromNode() argument
72 return SDDbgOperand(Node, ResNo); in fromNode()
106 unsigned ResNo; ///< Valid for expressions. member
116 u.s.ResNo = R; in SDDbgOperand()
H A DLegalizeTypes.h223 /// input operand, except for the result 'ResNo', for which the corresponding
225 SDValue DisintegrateMERGE_VALUES(SDNode *N, unsigned ResNo);
304 void PromoteIntegerResult(SDNode *N, unsigned ResNo);
305 SDValue PromoteIntRes_MERGE_VALUES(SDNode *N, unsigned ResNo);
310 SDValue PromoteIntRes_AtomicCmpSwap(AtomicSDNode *N, unsigned ResNo);
346 SDValue PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo);
360 SDValue PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo);
361 SDValue PromoteIntRes_UADDSUBO_CARRY(SDNode *N, unsigned ResNo);
362 SDValue PromoteIntRes_SADDSUBO_CARRY(SDNode *N, unsigned ResNo);
366 SDValue PromoteIntRes_XMULO(SDNode *N, unsigned ResNo);
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H A DLegalizeFloatTypes.cpp51 void DAGTypeLegalizer::SoftenFloatResult(SDNode *N, unsigned ResNo) { in SoftenFloatResult() argument
52 LLVM_DEBUG(dbgs() << "Soften float result " << ResNo << ": "; N->dump(&DAG)); in SoftenFloatResult()
59 dbgs() << "SoftenFloatResult #" << ResNo << ": "; in SoftenFloatResult()
66 case ISD::MERGE_VALUES:R = SoftenFloatRes_MERGE_VALUES(N, ResNo); break; in SoftenFloatResult()
71 R = SoftenFloatRes_EXTRACT_VECTOR_ELT(N, ResNo); break; in SoftenFloatResult()
176 SetSoftenedFloat(SDValue(N, ResNo), R); in SoftenFloatResult()
238 unsigned ResNo) { in SoftenFloatRes_MERGE_VALUES() argument
239 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo); in SoftenFloatRes_MERGE_VALUES()
285 SDValue DAGTypeLegalizer::SoftenFloatRes_EXTRACT_VECTOR_ELT(SDNode *N, unsigned ResNo) { in SoftenFloatRes_EXTRACT_VECTOR_ELT() argument
1372 void DAGTypeLegalizer::ExpandFloatResult(SDNode *N, unsigned ResNo) { in ExpandFloatResult() argument
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H A DLegalizeTypesGeneric.cpp34 void DAGTypeLegalizer::ExpandRes_MERGE_VALUES(SDNode *N, unsigned ResNo, in ExpandRes_MERGE_VALUES() argument
36 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo); in ExpandRes_MERGE_VALUES()
500 void DAGTypeLegalizer::SplitRes_MERGE_VALUES(SDNode *N, unsigned ResNo, in SplitRes_MERGE_VALUES() argument
502 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo); in SplitRes_MERGE_VALUES()
H A DInstrEmitter.h47 void EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone,
H A DLegalizeVectorTypes.cpp41 void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) { in ScalarizeVectorResult() argument
42 LLVM_DEBUG(dbgs() << "Scalarize node result " << ResNo << ": "; in ScalarizeVectorResult()
49 dbgs() << "ScalarizeVectorResult #" << ResNo << ": "; in ScalarizeVectorResult()
56 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break; in ScalarizeVectorResult()
135 R = ScalarizeVecRes_FFREXP(N, ResNo); in ScalarizeVectorResult()
215 R = ScalarizeVecRes_OverflowOp(N, ResNo); in ScalarizeVectorResult()
231 SetScalarizedVector(SDValue(N, ResNo), R); in ScalarizeVecRes_BinOp()
278 SDValue DAGTypeLegalizer::ScalarizeVecRes_FFREXP(SDNode *N, unsigned ResNo) { in ScalarizeVecRes_FFREXP()
293 unsigned OtherNo = 1 - ResNo; in ScalarizeVecRes_FFREXP()
303 return SDValue(ScalarNode, ResNo); in ScalarizeVecRes_StrictFPOp()
274 ScalarizeVecRes_FFREXP(SDNode * N,unsigned ResNo) ScalarizeVecRes_FFREXP() argument
341 ScalarizeVecRes_OverflowOp(SDNode * N,unsigned ResNo) ScalarizeVecRes_OverflowOp() argument
379 ScalarizeVecRes_MERGE_VALUES(SDNode * N,unsigned ResNo) ScalarizeVecRes_MERGE_VALUES() argument
1052 SplitVectorResult(SDNode * N,unsigned ResNo) SplitVectorResult() argument
1858 SplitVecRes_OverflowOp(SDNode * N,unsigned ResNo,SDValue & Lo,SDValue & Hi) SplitVecRes_OverflowOp() argument
2519 SplitVecRes_FFREXP(SDNode * N,unsigned ResNo,SDValue & Lo,SDValue & Hi) SplitVecRes_FFREXP() argument
4277 WidenVectorResult(SDNode * N,unsigned ResNo) WidenVectorResult() argument
4965 WidenVecRes_OverflowOp(SDNode * N,unsigned ResNo) WidenVecRes_OverflowOp() argument
5322 WidenVecRes_MERGE_VALUES(SDNode * N,unsigned ResNo) WidenVecRes_MERGE_VALUES() argument
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H A DInstrEmitter.cpp84 void InstrEmitter::EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, in EmitCopyFromReg() argument
90 SDValue Op(Node, ResNo); in EmitCopyFromReg()
103 MVT VT = Node->getSimpleValueType(ResNo); in EmitCopyFromReg()
113 User->getOperand(2).getResNo() == ResNo) { in EmitCopyFromReg()
123 if (Op.getNode() != Node || Op.getResNo() != ResNo) in EmitCopyFromReg()
178 SDValue Op(Node, ResNo); in EmitCopyFromReg()
H A DLegalizeIntegerTypes.cpp41 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) { in PromoteIntegerResult() argument
46 if (CustomLowerNode(N, N->getValueType(ResNo), true)) { in PromoteIntegerResult()
54 dbgs() << "PromoteIntegerResult #" << ResNo << ": "; in PromoteIntegerResult()
58 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break; in PromoteIntegerResult()
214 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break; in PromoteIntegerResult()
216 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break; in PromoteIntegerResult()
218 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break; in PromoteIntegerResult()
223 case ISD::USUBO_CARRY: Res = PromoteIntRes_UADDSUBO_CARRY(N, ResNo); break; in PromoteIntegerResult()
226 case ISD::SSUBO_CARRY: Res = PromoteIntRes_SADDSUBO_CARRY(N, ResNo); break; in PromoteIntegerResult()
279 Res = PromoteIntRes_AtomicCmpSwap(cast<AtomicSDNode>(N), ResNo); in PromoteIntegerResult()
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H A DLegalizeTypes.cpp975 SDValue DAGTypeLegalizer::DisintegrateMERGE_VALUES(SDNode *N, unsigned ResNo) { in DisintegrateMERGE_VALUES() argument
977 if (i != ResNo) in DisintegrateMERGE_VALUES()
979 return SDValue(N->getOperand(ResNo)); in DisintegrateMERGE_VALUES()
H A DScheduleDAGSDNodes.cpp126 unsigned ResNo = User->getOperand(2).getResNo(); in CheckForPhysRegDependency() local
132 if (ResNo >= II.getNumDefs() && II.hasImplicitDefOfPhysReg(Reg)) in CheckForPhysRegDependency()
138 TRI->getMinimalPhysRegClass(Reg, Def->getSimpleValueType(ResNo)); in CheckForPhysRegDependency()
H A DTargetLowering.cpp5695 unsigned ResNo = 0; // ResNo - The result number of the next output. in ParseConstraints() local
5722 getSimpleValueType(DL, STy->getElementType(ResNo)); in ParseConstraints()
5724 assert(ResNo == 0 && "Asm only has one result!"); in ParseConstraints()
5728 ++ResNo; in ParseConstraints()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAGNodes.h149 unsigned ResNo = 0; // Which return value of the node we are using.
156 unsigned getResNo() const { return ResNo; }
167 return Node == O.Node && ResNo == O.ResNo;
173 return std::tie(Node, ResNo) < std::tie(O.Node, O.ResNo);
242 V.ResNo = -1U;
248 V.ResNo = -2U;
1031 EVT getValueType(unsigned ResNo) const {
1032 assert(ResNo < NumValues && "Illegal result number!");
1033 return ValueList[ResNo];
1037 MVT getSimpleValueType(unsigned ResNo) const {
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DInlineAsmLowering.cpp236 unsigned ResNo = 0; // ResNo - The result number of the next output. in lowerInlineAsm() local
273 TLI->getSimpleValueType(DL, STy->getElementType(ResNo)); in lowerInlineAsm()
275 assert(ResNo == 0 && "Asm only has one result!"); in lowerInlineAsm()
279 ++ResNo; in lowerInlineAsm()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DDAGISelMatcherGen.cpp1065 for (unsigned ResNo = 0; ResNo < Pattern.getDstPattern().getNumResults(); in EmitResultCode() local
1066 ++ResNo) { in EmitResultCode()
1067 Results[ResNo] = Ops[Pattern.getDstPattern().getResultIndex(ResNo)]; in EmitResultCode()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp15536 unsigned ResNo = Op0.getResNo(); in PerformExtractEltToVMOVRRD() local
15546 V->getOperand(0).getResNo() == ResNo; in PerformExtractEltToVMOVRRD()
16434 unsigned ResNo = UI.getUse().getResNo(); in CombineVLDDUP() local
16436 if (ResNo == NumVecs) in CombineVLDDUP()
16439 DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo)); in CombineVLDDUP()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp16489 unsigned ResNo = User->getOperand(Op).getResNo(); in checkForPhysRegDependency() local
16490 if (User->getOperand(Op)->getValueType(ResNo) != MVT::i1) in checkForPhysRegDependency()
16496 TRI->getMinimalPhysRegClass(PhysReg, Def->getSimpleValueType(ResNo)); in checkForPhysRegDependency()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp45310 unsigned ResNo = InputVector.getResNo(); in combineExtractVectorElt() local
45311 auto IsBoolExtract = [&BoolExtracts, &ResNo, &IsVar](SDNode *Use) { in combineExtractVectorElt()
45313 Use->getOperand(0).getResNo() == ResNo && in combineExtractVectorElt()