| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64AddressingModes.h | 831 inline static bool isAnyMOVZMovAlias(uint64_t Value, int RegWidth) { in isAnyMOVZMovAlias() argument
832 for (int Shift = 0; Shift <= RegWidth - 16; Shift += 16) in isAnyMOVZMovAlias()
839 inline static bool isMOVZMovAlias(uint64_t Value, int Shift, int RegWidth) { in isMOVZMovAlias() argument
840 if (RegWidth == 32) in isMOVZMovAlias()
850 inline static bool isMOVNMovAlias(uint64_t Value, int Shift, int RegWidth) { in isMOVNMovAlias() argument
852 if (isAnyMOVZMovAlias(Value, RegWidth)) in isMOVNMovAlias()
856 if (RegWidth == 32) in isMOVNMovAlias()
859 return isMOVZMovAlias(Value, Shift, RegWidth); in isMOVNMovAlias()
862 inline static bool isAnyMOVWMovAlias(uint64_t Value, int RegWidth) { in isAnyMOVWMovAlias() argument
863 if (isAnyMOVZMovAlias(Value, RegWidth)) in isAnyMOVWMovAlias()
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| H A D | AArch64InstPrinter.cpp | 299 auto PrintMovImm = [&](uint64_t Value, int RegWidth) { in printInst() argument
300 int64_t SExtVal = SignExtend64(Value, RegWidth); in printInst()
310 uint64_t Mask = maskTrailingOnes<uint64_t>(RegWidth); in printInst()
323 int RegWidth = Opcode == AArch64::MOVZXi ? 64 : 32; in printInst() local
329 PrintMovImm(Value, RegWidth); in printInst()
336 int RegWidth = Opcode == AArch64::MOVNXi ? 64 : 32; in printInst() local
339 if (RegWidth == 32) in printInst()
342 if (AArch64_AM::isMOVNMovAlias(Value, Shift, RegWidth)) { in printInst()
343 PrintMovImm(Value, RegWidth); in printInst()
352 int RegWidth = Opcode == AArch64::ORRXri ? 64 : 32; in printInst() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64RegisterInfo.td | 1668 class ZPRExtendAsmOperand<string ShiftExtend, int RegWidth, int Scale,
1670 let Name = "ZPRExtend" # ShiftExtend # RegWidth # Scale
1674 # RegWidth # ", AArch64::ZPRRegClassID, "
1679 let DiagnosticType = "InvalidZPR" # RegWidth # ShiftExtend # Scale;
1685 int RegWidth, int Scale, string Suffix = "">
1688 !cast<AsmOperandClass>("ZPR" # RegWidth # "AsmOpndExt" # Repr # Scale # Suffix);
1693 # !if(!eq(RegWidth, 32), "'s'", "'d'") # ">";
1696 foreach RegWidth = [32, 64] in {
1698 def ZPR#RegWidth#AsmOpndExtUXTW8Only : ZPRExtendAsmOperand<"UXTW", RegWidth, 8, 0b1>;
1699 def ZPR#RegWidth#AsmOpndExtUXTW8 : ZPRExtendAsmOperand<"UXTW", RegWidth, 8>;
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| H A D | AArch64ISelDAGToDAG.cpp | 475 template<unsigned RegWidth>
477 return SelectCVTFixedPosOperand(N, FixedPos, RegWidth); in SelectCVTFixedPosOperand()
482 template<unsigned RegWidth>
484 return SelectCVTFixedPosRecipOperand(N, FixedPos, RegWidth); in SelectCVTFixedPosRecipOperand()
3957 unsigned RegWidth, in checkCVTFixedPointOperandWithFBits() argument
3999 if (FBits == 0 || FBits > RegWidth) return false; in checkCVTFixedPointOperandWithFBits()
4006 unsigned RegWidth) { in SelectCVTFixedPosOperand() argument
4007 return checkCVTFixedPointOperandWithFBits(CurDAG, N, FixedPos, RegWidth, in SelectCVTFixedPosOperand()
4013 unsigned RegWidth) { in SelectCVTFixedPosRecipOperand() argument
4014 return checkCVTFixedPointOperandWithFBits(CurDAG, N, FixedPos, RegWidth, in SelectCVTFixedPosRecipOperand()
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| H A D | AArch64TargetTransformInfo.cpp | 3814 auto RegWidth = in getVectorInstrCostHelper() local
3817 return Idx == 0 || (RegWidth != 0 && (Idx * EltSz) % RegWidth == 0); in getVectorInstrCostHelper()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonTargetTransformInfo.cpp | 184 unsigned RegWidth = in getMemoryOpCost() local
187 assert(RegWidth && "Non-zero vector register width expected"); in getMemoryOpCost()
189 if (VecWidth % RegWidth == 0) in getMemoryOpCost()
190 return VecWidth / RegWidth; in getMemoryOpCost()
192 const Align RegAlign(RegWidth / 8); in getMemoryOpCost()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 1334 unsigned RegWidth) { in usesRegister() argument
1337 usesSgprAt(DwordRegIndex + divideCeil(RegWidth, 32) - 1); in usesRegister()
1340 usesAgprAt(DwordRegIndex + divideCeil(RegWidth, 32) - 1); in usesRegister()
1343 usesVgprAt(DwordRegIndex + divideCeil(RegWidth, 32) - 1); in usesRegister()
1414 bool AddNextRegisterToList(MCRegister &Reg, unsigned &RegWidth,
1417 unsigned &RegNum, unsigned &RegWidth,
1420 unsigned &RegNum, unsigned &RegWidth,
1423 unsigned &RegWidth,
1426 unsigned &RegWidth,
1429 unsigned &RegWidth,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 1161 template<int RegWidth, int Shift>
1169 return AArch64_AM::isMOVZMovAlias(Value, Shift, RegWidth); in isMOVZMovAlias()
1176 template<int RegWidth, int Shift>
1184 return AArch64_AM::isMOVNMovAlias(Value, Shift, RegWidth); in isMOVNMovAlias()
6451 uint64_t RegWidth = 0; in matchAndEmitInstruction() local
6454 RegWidth = 64; in matchAndEmitInstruction()
6456 RegWidth = 32; in matchAndEmitInstruction()
6458 if (LSB >= RegWidth) in matchAndEmitInstruction()
6461 if (Width < 1 || Width > RegWidth) in matchAndEmitInstruction()
6466 if (RegWidth == 32) in matchAndEmitInstruction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.cpp | 1593 const unsigned RegWidth = AMDGPU::getRegBitWidth(*RC) / 8; in buildSpillLoadStore() local
1598 unsigned EltSize = IsBlock ? RegWidth in buildSpillLoadStore()
1599 : (IsFlat && !IsAGPR) ? std::min(RegWidth, 16u) in buildSpillLoadStore()
1601 unsigned NumSubRegs = RegWidth / EltSize; in buildSpillLoadStore()
1603 unsigned RemSize = RegWidth - Size; in buildSpillLoadStore()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 1814 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits(); variable
1815 return (BitWidth + RegWidth - 1) / RegWidth;
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | CodeGenPrepare.cpp | 7820 unsigned RegWidth = RegType.getSizeInBits(); in optimizeSwitchType() local
7822 if (RegWidth <= cast<IntegerType>(OldType)->getBitWidth()) in optimizeSwitchType()
7831 auto *NewType = Type::getIntNTy(Context, RegWidth); in optimizeSwitchType()
7856 ? NarrowConst.zext(RegWidth) in optimizeSwitchType()
7857 : NarrowConst.sext(RegWidth); in optimizeSwitchType()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVTargetTransformInfo.cpp | 2644 TypeSize RegWidth = in getMaximumVF() local
2648 return std::max<unsigned>(1U, RegWidth.getFixedValue() / ElemWidth); in getMaximumVF()
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