| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64AddressingModes.h | 831 inline static bool isAnyMOVZMovAlias(uint64_t Value, int RegWidth) { in isMOVNMovAlias()
832 for (int Shift = 0; Shift <= RegWidth - 16; Shift += 16) in isMOVNMovAlias()
839 inline static bool isMOVZMovAlias(uint64_t Value, int Shift, int RegWidth) { in isMOVNMovAlias()
840 if (RegWidth == 32)
850 inline static bool isMOVNMovAlias(uint64_t Value, int Shift, int RegWidth) { in isAnyMOVWMovAlias()
852 if (isAnyMOVZMovAlias(Value, RegWidth))
856 if (RegWidth == 32)
859 return isMOVZMovAlias(Value, Shift, RegWidth);
862 inline static bool isAnyMOVWMovAlias(uint64_t Value, int RegWidth) {
863 if (isAnyMOVZMovAlias(Value, RegWidth))
810 isAnyMOVZMovAlias(uint64_t Value,int RegWidth) isAnyMOVZMovAlias() argument
818 isMOVZMovAlias(uint64_t Value,int Shift,int RegWidth) isMOVZMovAlias() argument
829 isMOVNMovAlias(uint64_t Value,int Shift,int RegWidth) isMOVNMovAlias() argument
841 isAnyMOVWMovAlias(uint64_t Value,int RegWidth) isAnyMOVWMovAlias() argument
[all...] |
| H A D | AArch64InstPrinter.cpp | 300 auto PrintMovImm = [&](uint64_t Value, int RegWidth) { in printInst()
301 int64_t SExtVal = SignExtend64(Value, RegWidth); in printInst()
311 uint64_t Mask = maskTrailingOnes<uint64_t>(RegWidth); in printInst()
324 int RegWidth = Opcode == AArch64::MOVZXi ? 64 : 32; in printInst()
330 PrintMovImm(Value, RegWidth); in printInst()
337 int RegWidth = Opcode == AArch64::MOVNXi ? 64 : 32; in printInst()
340 if (RegWidth == 32) in printInst()
343 if (AArch64_AM::isMOVNMovAlias(Value, Shift, RegWidth)) { in printInst()
344 PrintMovImm(Value, RegWidth); in printInst()
353 int RegWidth in printInst()
285 __anonc553032e0102(uint64_t Value, int RegWidth) printInst() argument
309 int RegWidth = Opcode == AArch64::MOVZXi ? 64 : 32; printInst() local
322 int RegWidth = Opcode == AArch64::MOVNXi ? 64 : 32; printInst() local
338 int RegWidth = Opcode == AArch64::ORRXri ? 64 : 32; printInst() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64RegisterInfo.td | 1518 class ZPRExtendAsmOperand<string ShiftExtend, int RegWidth, int Scale,
1520 let Name = "ZPRExtend" # ShiftExtend # RegWidth # Scale
1524 # RegWidth # ", AArch64::ZPRRegClassID, "
1529 let DiagnosticType = "InvalidZPR" # RegWidth # ShiftExtend # Scale;
1535 int RegWidth, int Scale, string Suffix = "">
1538 !cast<AsmOperandClass>("ZPR" # RegWidth # "AsmOpndExt" # Repr # Scale # Suffix);
1543 # !if(!eq(RegWidth, 32), "'s'", "'d'") # ">";
1546 foreach RegWidth = [32, 64] in {
1548 def ZPR#RegWidth#AsmOpndExtUXTW8Only : ZPRExtendAsmOperand<"UXTW", RegWidth, 8, 0b1>;
1549 def ZPR#RegWidth#AsmOpndExtUXTW8 : ZPRExtendAsmOperand<"UXTW", RegWidth, 8>;
[all …]
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| H A D | AArch64ISelDAGToDAG.cpp | 477 template<unsigned RegWidth>
479 return SelectCVTFixedPosOperand(N, FixedPos, RegWidth); in SelectCVTFixedPosOperand()
484 template<unsigned RegWidth>
486 return SelectCVTFixedPosRecipOperand(N, FixedPos, RegWidth); in SelectCVTFixedPosRecipOperand()
3855 unsigned RegWidth, in checkCVTFixedPointOperandWithFBits() argument
3897 if (FBits == 0 || FBits > RegWidth) return false; in checkCVTFixedPointOperandWithFBits()
3904 unsigned RegWidth) { in SelectCVTFixedPosOperand() argument
3905 return checkCVTFixedPointOperandWithFBits(CurDAG, N, FixedPos, RegWidth, in SelectCVTFixedPosOperand()
3911 unsigned RegWidth) { in SelectCVTFixedPosRecipOperand() argument
3912 return checkCVTFixedPointOperandWithFBits(CurDAG, N, FixedPos, RegWidth, in SelectCVTFixedPosRecipOperand()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonTargetTransformInfo.cpp | 183 unsigned RegWidth = in getMemoryOpCost() local
186 assert(RegWidth && "Non-zero vector register width expected"); in getMemoryOpCost()
188 if (VecWidth % RegWidth == 0) in getMemoryOpCost()
189 return VecWidth / RegWidth; in getMemoryOpCost()
191 const Align RegAlign(RegWidth / 8); in getMemoryOpCost()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 1281 unsigned RegWidth) { in usesRegister() argument
1284 usesSgprAt(DwordRegIndex + divideCeil(RegWidth, 32) - 1); in usesRegister()
1287 usesAgprAt(DwordRegIndex + divideCeil(RegWidth, 32) - 1); in usesRegister()
1290 usesVgprAt(DwordRegIndex + divideCeil(RegWidth, 32) - 1); in usesRegister()
1361 bool AddNextRegisterToList(unsigned& Reg, unsigned& RegWidth,
1364 unsigned &RegNum, unsigned &RegWidth,
1367 unsigned &RegNum, unsigned &RegWidth,
1370 unsigned &RegWidth,
1373 unsigned &RegWidth,
1376 unsigned &RegWidth, SmallVectorImpl<AsmToken> &Tokens);
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 1142 template<int RegWidth, int Shift>
1150 return AArch64_AM::isMOVZMovAlias(Value, Shift, RegWidth); in isMOVZMovAlias()
1157 template<int RegWidth, int Shift>
1165 return AArch64_AM::isMOVNMovAlias(Value, Shift, RegWidth); in isMOVNMovAlias()
6262 uint64_t RegWidth = 0; in MatchAndEmitInstruction() local
6265 RegWidth = 64; in MatchAndEmitInstruction()
6267 RegWidth = 32; in MatchAndEmitInstruction()
6269 if (LSB >= RegWidth) in MatchAndEmitInstruction()
6272 if (Width < 1 || Width > RegWidth) in MatchAndEmitInstruction()
6277 if (RegWidth == 32) in MatchAndEmitInstruction()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.cpp | 1352 const unsigned RegWidth = AMDGPU::getRegBitWidth(*RC) / 8; in buildSpillLoadStore() local
1356 unsigned EltSize = (IsFlat && !IsAGPR) ? std::min(RegWidth, 16u) : 4u; in buildSpillLoadStore()
1357 unsigned NumSubRegs = RegWidth / EltSize; in buildSpillLoadStore()
1359 unsigned RemSize = RegWidth - Size; in buildSpillLoadStore()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVTargetTransformInfo.cpp | 1926 TypeSize RegWidth = in getMaximumVF() local
1930 return std::max<unsigned>(1U, RegWidth.getFixedValue() / ElemWidth); in getMaximumVF()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 1761 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits(); variable
1762 return (BitWidth + RegWidth - 1) / RegWidth;
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | CodeGenPrepare.cpp | 7428 unsigned RegWidth = RegType.getSizeInBits(); in optimizeSwitchType() local
7430 if (RegWidth <= cast<IntegerType>(OldType)->getBitWidth()) in optimizeSwitchType()
7439 auto *NewType = Type::getIntNTy(Context, RegWidth); in optimizeSwitchType()
7464 ? NarrowConst.zext(RegWidth) in optimizeSwitchType()
7465 : NarrowConst.sext(RegWidth); in optimizeSwitchType()
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