Lines Matching refs:RegWidth
1142 template<int RegWidth, int Shift>
1150 return AArch64_AM::isMOVZMovAlias(Value, Shift, RegWidth); in isMOVZMovAlias()
1157 template<int RegWidth, int Shift>
1165 return AArch64_AM::isMOVNMovAlias(Value, Shift, RegWidth); in isMOVNMovAlias()
6262 uint64_t RegWidth = 0; in MatchAndEmitInstruction() local
6265 RegWidth = 64; in MatchAndEmitInstruction()
6267 RegWidth = 32; in MatchAndEmitInstruction()
6269 if (LSB >= RegWidth) in MatchAndEmitInstruction()
6272 if (Width < 1 || Width > RegWidth) in MatchAndEmitInstruction()
6277 if (RegWidth == 32) in MatchAndEmitInstruction()
6293 RegWidth == 32 ? AArch64::WZR : AArch64::XZR, RegKind::Scalar, in MatchAndEmitInstruction()
6318 uint64_t RegWidth = 0; in MatchAndEmitInstruction() local
6321 RegWidth = 64; in MatchAndEmitInstruction()
6323 RegWidth = 32; in MatchAndEmitInstruction()
6325 if (Op3Val >= RegWidth) in MatchAndEmitInstruction()
6328 if (Op4Val < 1 || Op4Val > RegWidth) in MatchAndEmitInstruction()
6333 if (RegWidth == 32) in MatchAndEmitInstruction()
6382 uint64_t RegWidth = 0; in MatchAndEmitInstruction() local
6385 RegWidth = 64; in MatchAndEmitInstruction()
6387 RegWidth = 32; in MatchAndEmitInstruction()
6389 if (Op3Val >= RegWidth) in MatchAndEmitInstruction()
6392 if (Op4Val < 1 || Op4Val > RegWidth) in MatchAndEmitInstruction()
6398 if (NewOp4Val >= RegWidth || NewOp4Val < Op3Val) in MatchAndEmitInstruction()