| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchFloat32InstrInfo.td | 156 class PatFpr<SDPatternOperator OpNode, LAInst Inst, RegisterClass RegTy>
157 : Pat<(OpNode RegTy:$fj), (Inst $fj)>;
158 class PatFprFpr<SDPatternOperator OpNode, LAInst Inst, RegisterClass RegTy>
159 : Pat<(OpNode RegTy:$fj, RegTy:$fk), (Inst $fj, $fk)>;
185 class PatFPSetcc<CondCode cc, LAInst CmpInst, RegisterClass RegTy>
186 : Pat<(any_fsetcc RegTy:$fj, RegTy:$fk, cc),
187 (CmpInst RegTy:$fj, RegTy
[all...] |
| /freebsd/contrib/llvm-project/clang/lib/StaticAnalyzer/Checkers/ |
| H A D | BoolAssignmentChecker.cpp | 67 QualType RegTy = TR->getValueType(); in checkBind() local
69 if (!isBooleanType(RegTy)) in checkBind()
86 llvm::APSInt Zero = BVF.getValue(0, RegTy); in checkBind()
87 llvm::APSInt One = BVF.getValue(1, RegTy); in checkBind()
|
| /freebsd/contrib/llvm-project/clang/lib/CodeGen/Targets/ |
| H A D | BPF.cpp | 40 llvm::Type *RegTy = llvm::IntegerType::get(getVMContext(), 64); in classifyArgumentType() local
41 CoerceTy = llvm::ArrayType::get(RegTy, 2); in classifyArgumentType()
|
| H A D | PPC.cpp | 881 llvm::Type *RegTy = llvm::IntegerType::get(getVMContext(), RegBits); in classifyArgumentType() local
882 CoerceTy = llvm::ArrayType::get(RegTy, NumRegs); in classifyArgumentType()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsRegisterBankInfo.cpp | 432 LLT RegTy = MRI.getType(Op.getReg()); in getInstrMapping() local
434 if (RegTy.isScalar() && in getInstrMapping()
435 (RegTy.getSizeInBits() != 32 && RegTy.getSizeInBits() != 64)) in getInstrMapping()
438 if (RegTy.isVector() && RegTy.getSizeInBits() != 128) in getInstrMapping()
|
| H A D | MipsCallLowering.cpp | 428 LLT RegTy = LLT::scalar(RegSize * 8); in lowerFormalArguments() local
430 MIRBuilder.buildCopy(RegTy, Register(ArgRegs[I])); in lowerFormalArguments()
437 MPO, MachineMemOperand::MOStore, RegTy, Align(RegSize)); in lowerFormalArguments()
|
| H A D | MipsISelLowering.cpp | 4401 MVT RegTy = MVT::getIntegerVT(GPRSizeInBytes * 8); in copyByValRegs() local
4402 const TargetRegisterClass *RC = getRegClassFor(RegTy); in copyByValRegs()
4410 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy), in copyByValRegs()
4430 RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); in passByValArg() local
4442 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr, in passByValArg()
4469 ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(), in passByValArg()
4481 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal, in passByValArg()
4485 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift); in passByValArg()
4520 MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); in writeVarArgRegs() local
4521 const TargetRegisterClass *RC = getRegClassFor(RegTy); in writeVarArgRegs()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | Utils.cpp | 502 bool llvm::extractParts(Register Reg, LLT RegTy, LLT MainTy, LLT &LeftoverTy, in extractParts() argument
509 unsigned RegSize = RegTy.getSizeInBits(); in extractParts()
527 if (RegTy.isVector() && MainTy.isVector()) { in extractParts()
528 unsigned RegNumElts = RegTy.getNumElements(); in extractParts()
534 RegTy.getScalarSizeInBits() == MainTy.getScalarSizeInBits() && in extractParts()
537 LLT::fixed_vector(LeftoverNumElts, RegTy.getScalarSizeInBits()); in extractParts()
601 LLT RegTy = MRI.getType(Reg); in extractVectorParts() local
602 assert(RegTy.isVector() && "Expected a vector type"); in extractVectorParts()
604 LLT EltTy = RegTy.getElementType(); in extractVectorParts()
606 unsigned RegNumElts = RegTy.getNumElements(); in extractVectorParts()
[all …]
|
| H A D | RegBankSelect.cpp | 174 LLT RegTy = MRI->getType(MO.getReg()); in repairReg() local
177 if (RegTy.isVector()) { in repairReg()
178 if (ValMapping.NumBreakDowns == RegTy.getNumElements()) in repairReg()
183 RegTy.getSizeInBits()) && in repairReg()
184 (ValMapping.BreakDown[0].Length % RegTy.getScalarSizeInBits() == in repairReg()
|
| H A D | CallLowering.cpp | 1388 const LLT RegTy = MRI.getType(ValVReg); in assignValueToReg() local
1390 if (isCopyCompatibleType(RegTy, LocTy)) { in assignValueToReg()
1396 auto Hint = buildExtensionHint(VA, Copy.getReg(0), RegTy); in assignValueToReg()
|
| H A D | CombinerHelper.cpp | 920 LLT RegTy = MRI.getType(LoadReg); in matchCombineLoadWithAndMask() local
922 unsigned RegSize = RegTy.getSizeInBits(); in matchCombineLoadWithAndMask()
954 {TargetOpcode::G_ZEXTLOAD, {RegTy, MRI.getType(PtrReg)}, {MemDesc}})) in matchCombineLoadWithAndMask()
1034 LLT RegTy = MRI.getType(DstReg); in matchSextInRegOfLoad() local
1037 if (RegTy.isVector()) in matchSextInRegOfLoad()
1067 else if (MemBits > NewSizeBits || MemBits == RegTy.getSizeInBits()) in matchSextInRegOfLoad()
|
| H A D | LegalizerHelper.cpp | 5923 LLT RegTy = MRI.getType(MI.getOperand(0).getReg()); in narrowScalarAddSub() local
5926 extractParts(Src1, RegTy, NarrowTy, LeftoverTy, Src1Regs, Src1Left, in narrowScalarAddSub()
5928 extractParts(Src2, RegTy, NarrowTy, DummyTy, Src2Regs, Src2Left, MIRBuilder, in narrowScalarAddSub()
5960 insertParts(MI.getOperand(0).getReg(), RegTy, NarrowTy, in narrowScalarAddSub()
6100 LLT RegTy = MRI.getType(MI.getOperand(0).getReg()); in narrowScalarInsert() local
6102 extractParts(MI.getOperand(1).getReg(), RegTy, NarrowTy, LeftoverTy, SrcRegs, in narrowScalarInsert()
6164 if (WideSize > RegTy.getSizeInBits()) { in narrowScalarInsert()
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineRegisterInfo.cpp | 96 const LLT RegTy = getType(Reg); in constrainRegAttrs() local
98 if (RegTy.isValid() && ConstrainingRegTy.isValid() && in constrainRegAttrs()
99 RegTy != ConstrainingRegTy) in constrainRegAttrs()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstructionSelector.cpp | |
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/ |
| H A D | X86InstructionSelector.cpp | 1621 const LLT RegTy = MRI.getType(DstReg); in selectMulDivRem() local
1622 assert(RegTy == MRI.getType(Op1Reg) && RegTy == MRI.getType(Op2Reg) && in selectMulDivRem()
1709 auto OpEntryIt = llvm::find_if(OpTable, [RegTy](const MulDivRemEntry &El) { in selectMulDivRem()
1710 return El.SizeInBits == RegTy.getSizeInBits(); in selectMulDivRem()
1746 const TargetRegisterClass *RegRC = getRegClass(RegTy, *RegRB); in selectMulDivRem()
1773 if (RegTy.getSizeInBits() == 16) { in selectMulDivRem()
1777 } else if (RegTy.getSizeInBits() == 32) { in selectMulDivRem()
1781 } else if (RegTy.getSizeInBits() == 64) { in selectMulDivRem()
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | Utils.h | 259 bool extractParts(Register Reg, LLT RegTy, LLT MainTy, LLT &LeftoverTy,
350 const DebugLoc &DL, LLT RegTy = LLT());
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfoF.td | 491 DAGOperand RegTy, ValueType vt>
492 : Pat<(OpNode (vt RegTy:$rs1), (vt RegTy:$rs2)), (Inst $rs1, $rs2)>;
501 DAGOperand RegTy, ValueType vt>
502 : Pat<(OpNode (vt RegTy:$rs1), (vt RegTy:$rs2)), (Inst $rs1, $rs2, FRM_DYN)>;
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstrNEON.td | 4817 class VDOT<bit op6, bit op4, bit op23, RegisterClass RegTy, string Asm,
4820 N3Vnp<{0b1100, op23}, 0b10, 0b1101, op6, op4, (outs RegTy:$dst),
4821 (ins RegTy:$Vd, RegTy:$Vn, RegTy:$Vm), N3RegFrm, IIC_VDOTPROD,
4823 [(set (AccumTy RegTy:$dst),
4824 (OpNode (AccumTy RegTy:$Vd),
4825 (InputTy RegTy:$Vn),
4826 (InputTy RegTy:$Vm)))]> {
4884 multiclass N3VMixedDotLane<bit Q, bit U, string Asm, string AsmTy, RegisterClass RegTy,
4888 def "" : N3Vnp<0b11101, 0b00, 0b1101, Q, U, (outs RegTy:$dst),
4889 (ins RegTy:$Vd, RegTy:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane), N3RegFrm,
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FrameLowering.cpp | 5118 unsigned RegTy = StackAccess::AccessType::GPR; in emitRemarks() local
5121 RegTy = StackAccess::PPR; in emitRemarks()
5123 RegTy = StackAccess::FPR; in emitRemarks()
5125 RegTy = StackAccess::FPR; in emitRemarks()
5128 StackAccesses[ArrIdx].AccessTypes |= RegTy; in emitRemarks()
5130 if (RegTy == StackAccess::FPR) in emitRemarks()
|
| H A D | AArch64ISelDAGToDAG.cpp | 4110 MVT RegTy = MemTy == MVT::i64 ? MVT::i64 : MVT::i32; in SelectCMP_SWAP() local
4115 CurDAG->getVTList(RegTy, MVT::i32, MVT::Other), Ops); in SelectCMP_SWAP()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/ |
| H A D | HexagonAsmParser.cpp | 207 struct RegTy { struct
217 struct RegTy Reg;
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 1839 template <VecListIndexType RegTy, unsigned NumRegs>
1856 assert((RegTy != VecListIdx_ZReg || NumRegs <= 4) && in addVectorListOperands()
1859 assert((RegTy != VecListIdx_PReg || NumRegs <= 2) && in addVectorListOperands()
1862 unsigned FirstReg = FirstRegs[(unsigned)RegTy][NumRegs]; in addVectorListOperands()
1864 FirstRegs[(unsigned)RegTy][0])); in addVectorListOperands()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPULegalizerInfo.cpp | 6561 LLT RegTy; in legalizeImageIntrinsic() local
6567 RegTy = S32; in legalizeImageIntrinsic()
6575 RegTy = !IsTFE && EltSize == 16 ? V2S16 : S32; in legalizeImageIntrinsic()
6629 ResultRegs[I] = MRI->createGenericVirtualRegister(RegTy); in legalizeImageIntrinsic()
6659 if (RegTy != V2S16 && !ST.hasUnpackedD16VMem()) { in legalizeImageIntrinsic()
|