| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | RegUsageInfoPropagate.cpp | 61 static void setRegMask(MachineInstr &MI, ArrayRef<uint32_t> RegMask) { in setRegMask() argument
62 assert(RegMask.size() == in setRegMask()
69 MO.setRegMask(RegMask.data()); in setRegMask()
122 const ArrayRef<uint32_t> RegMask = PRUI->getRegUsageInfo(F); in runOnMachineFunction() local
123 if (RegMask.empty()) in runOnMachineFunction()
125 setRegMask(MI, RegMask); in runOnMachineFunction()
|
| H A D | RegUsageInfoCollector.cpp | 122 std::vector<uint32_t> RegMask; in runOnMachineFunction() local
128 RegMask.resize(RegMaskSize, ~((uint32_t)0)); in runOnMachineFunction()
141 auto SetRegAsDefined = [&RegMask] (unsigned Reg) { in runOnMachineFunction()
142 RegMask[Reg / 32] &= ~(1u << Reg % 32); in runOnMachineFunction()
185 if (MachineOperand::clobbersPhysReg(&(RegMask[0]), PReg)) in runOnMachineFunction()
192 PRUI.storeUpdateRegUsageInfo(F, RegMask); in runOnMachineFunction()
|
| H A D | RegisterUsageInfo.cpp | 58 const Function &FP, ArrayRef<uint32_t> RegMask) { in storeUpdateRegUsageInfo() argument
59 RegMasks[&FP] = RegMask; in storeUpdateRegUsageInfo()
76 for (const auto &RegMask : RegMasks) in print() local
77 FPRMPairVector.push_back(&RegMask); in print()
|
| H A D | LiveRegUnits.cpp | 22 void LiveRegUnits::removeRegsNotPreserved(const uint32_t *RegMask) { in removeRegsNotPreserved() argument
25 if (MachineOperand::clobbersPhysReg(RegMask, *RootReg)) { in removeRegsNotPreserved()
33 void LiveRegUnits::addRegsInMask(const uint32_t *RegMask) { in addRegsInMask() argument
36 if (MachineOperand::clobbersPhysReg(RegMask, *RootReg)) { in addRegsInMask()
|
| H A D | MachineStableHash.cpp | 126 const uint32_t *RegMask = MO.getRegMask(); in stableHashValue() local
127 std::vector<llvm::stable_hash> RegMaskHashes(RegMask, in stableHashValue()
128 RegMask + RegMaskSize); in stableHashValue()
|
| H A D | MachineOperand.cpp | 354 const uint32_t *RegMask = getRegMask(); in isIdenticalTo() local
356 if (RegMask == OtherRegMask) in isIdenticalTo()
363 return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask); in isIdenticalTo()
424 const uint32_t *RegMask = MO.getRegMask(); in hash_value() local
425 std::vector<stable_hash> RegMaskHashes(RegMask, RegMask + RegMaskSize); in hash_value()
958 const uint32_t *RegMask = getRegLiveOut(); in print() local
965 if (RegMask[Reg / 32] & (1U << (Reg % 32))) { in print()
|
| H A D | MachineCopyPropagation.cpp | 875 const MachineOperand *RegMask = nullptr; in ForwardCopyPropagateBlock() local
878 RegMask = &MO; in ForwardCopyPropagateBlock()
898 if (RegMask) { in ForwardCopyPropagateBlock()
909 if (!RegMask->clobbersPhysReg(Reg)) { in ForwardCopyPropagateBlock()
|
| H A D | MIRPrinter.cpp | 268 static void printCustomRegMask(const uint32_t *RegMask, raw_ostream &OS, in printCustomRegMask() argument
270 assert(RegMask && "Can't print an empty register mask"); in printCustomRegMask()
276 if (RegMask[I / 32] & (1u << (I % 32))) { in printCustomRegMask()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/AsmParser/ |
| H A D | M68kAsmParser.cpp | 83 RegMask, enumerator
111 uint16_t RegMask; member
276 case Kind::RegMask: in print()
277 OS << "RegMask(" << format("%04x", RegMask) << ")"; in print()
385 if (MemOp.Op == M68kMemOp::Kind::RegMask) in isMoveMask()
400 uint16_t MoveMask = MemOp.RegMask; in addMoveMaskOperands()
893 M68kMemOp MemOp(M68kMemOp::Kind::RegMask); in parseRegOrMoveMask()
894 MemOp.RegMask = 0; in parseRegOrMoveMask()
898 (MemOp.Op == M68kMemOp::Kind::RegMask) && (MemOp.RegMask == 0); in parseRegOrMoveMask()
929 MemOp.Op = M68kMemOp::Kind::RegMask; in parseRegOrMoveMask()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MachineOperand.h | 174 const uint32_t *RegMask; // For MO_RegisterMask and MO_RegisterLiveOut. member
642 /// clobbersPhysReg - Returns true if this RegMask clobbers PhysReg.
646 static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg) { in clobbersPhysReg() argument
649 return !(RegMask[PhysReg / 32] & (1u << PhysReg % 32)); in clobbersPhysReg()
652 /// clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg.
657 /// getRegMask - Returns a bit mask of registers preserved by this RegMask
661 return Contents.RegMask; in getRegMask()
672 return Contents.RegMask; in getRegLiveOut()
738 Contents.RegMask = RegMaskPtr; in setRegMask()
924 /// A RegMask operan
[all...] |
| H A D | LiveRegUnits.h | 109 void removeRegsNotPreserved(const uint32_t *RegMask);
113 void addRegsInMask(const uint32_t *RegMask);
|
| H A D | RegisterUsageInfo.h | 52 ArrayRef<uint32_t> RegMask);
|
| H A D | MachineRegisterInfo.h | 903 void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) { in addPhysRegsUsedFromRegMask() argument
904 UsedPhysRegMask.setBitsNotInMask(RegMask); in addPhysRegsUsedFromRegMask()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64CollectLOH.cpp | 486 static void handleRegMaskClobber(const uint32_t *RegMask, MCPhysReg Reg, in handleADRP()
488 if (!MachineOperand::clobbersPhysReg(RegMask, Reg)) in handleADRP()
499 const uint32_t *RegMask = MO.getRegMask(); in handleNormalInst()
501 handleRegMaskClobber(RegMask, Reg, LOHInfos); in handleNormalInst()
503 handleRegMaskClobber(RegMask, Reg, LOHInfos); in handleNormalInst() local
490 handleRegMaskClobber(const uint32_t * RegMask,MCPhysReg Reg,LOHInfo * LOHInfos) handleRegMaskClobber() argument
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUCallingConv.td | 237 // Trivial class to denote when a def is used only to get a RegMask, i.e.
240 class RegMask<dag mask> : CalleeSavedRegs<mask>;
242 def AMDGPU_AllVGPRs : RegMask<
246 def AMDGPU_AllAGPRs : RegMask<
250 def AMDGPU_AllVectorRegs : RegMask<
254 def AMDGPU_AllAllocatableSRegs : RegMask<
|
| H A D | GCNRegPressure.cpp | 620 LaneBitmask RegMask = MRI.getMaxLaneMaskForVReg(Reg); in getRegLiveThroughMask() local
621 if ((RegMask & Mask) == RegMask && IsInOneSegment(LI)) in getRegLiveThroughMask()
622 LiveThroughMask = RegMask; in getRegLiveThroughMask()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kRegisterInfo.cpp | 153 const uint32_t *RegMask = getCallPreservedMask(MF, CC); in getReservedRegs() local
154 if (MachineOperand::clobbersPhysReg(RegMask, getBaseRegister())) in getReservedRegs()
|
| /freebsd/contrib/llvm-project/llvm/lib/ExecutionEngine/JITLink/ |
| H A D | aarch32.cpp | 347 uint16_t Hi = R.Hi & FixupInfo<Kind>::RegMask.Hi; in applyFixupThumb()
348 uint16_t Lo = R.Lo & FixupInfo<Kind>::RegMask.Lo; in applyFixupThumb()
354 uint32_t Wd = R.Wd & FixupInfo<Kind>::RegMask; in applyFixupThumb()
360 static constexpr HalfWords Mask = FixupInfo<Kind>::RegMask; in applyFixupThumb()
369 static constexpr uint32_t Mask = FixupInfo<Kind>::RegMask; in applyFixupThumb()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZElimCompare.cpp | 629 const uint32_t *RegMask; in fuseCompareOperations() local
631 RegMask = MBBI->getOperand(3).getRegMask(); in fuseCompareOperations()
669 MIB.addRegMask(RegMask); in fuseCompareOperations()
|
| /freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | VectorUtils.cpp | 539 SmallVectorImpl<int> &RegMask = Dest[I]; in processShuffleMasks() local
540 if (RegMask.empty()) in processShuffleMasks()
545 FirstMask = RegMask; in processShuffleMasks()
549 SecondMask = RegMask; in processShuffleMasks()
553 RegMask.clear(); in processShuffleMasks()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCCodeEmitter.cpp | 606 unsigned RegMask = MI.getOperand(OpIdx).getImm(); in getImm8OptLsl()
607 assert(RegMask <= 0xFF && "Invalid register mask!"); in getImm8OptLsl()
608 return RegMask;
577 unsigned RegMask = MI.getOperand(OpIdx).getImm(); EncodeMatrixTileListRegisterClass() local
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLoweringCall.cpp | 1097 uint32_t *RegMask) const { in LowerCallResult()
1114 if (RegMask) { in LowerCallResult()
1116 RegMask[SubReg / 32] &= ~(1u << (SubReg % 32)); in LowerCallResult()
2469 uint32_t *RegMask = nullptr; in LowerCall() local
2480 RegMask = MF.allocateRegMask(); in LowerCall()
2482 memcpy(RegMask, Mask, sizeof(RegMask[0]) * RegMaskSize); in LowerCall()
2489 RegMask[SubReg / 32] &= ~(1u << (SubReg % 32)); in LowerCall()
2493 Ops.push_back(DAG.getRegisterMask(RegMask)); in LowerCall()
2583 InVals, RegMask); in LowerCall()
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/ExecutionEngine/JITLink/ |
| H A D | aarch32.h | 199 /// RegMask - Mask with all bits set that encode the register
225 static constexpr uint32_t RegMask = 0x0000f000;
253 static constexpr HalfWords RegMask{0x0000, 0x0f00};
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ScheduleDAGRRList.cpp | 1321 static void CheckForLiveRegDefMasked(SUnit *SU, const uint32_t *RegMask, in CheckForLiveRegDefMasked() argument
1329 if (!MachineOperand::clobbersPhysReg(RegMask, i)) continue; in CheckForLiveRegDefMasked()
1417 if (const uint32_t *RegMask = getNodeRegMask(Node)) in DelayForLiveRegsBottomUp() local
1418 CheckForLiveRegDefMasked(SU, RegMask, in DelayForLiveRegsBottomUp()
2862 const uint32_t *RegMask = getNodeRegMask(SU->getNode()); in canClobberReachingPhysRegUse() local
2863 if (ImpDefs.empty() && !RegMask) in canClobberReachingPhysRegUse()
2872 if (RegMask && in canClobberReachingPhysRegUse()
2873 MachineOperand::clobbersPhysReg(RegMask, SuccPred.getReg()) && in canClobberReachingPhysRegUse()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMLowOverheadLoops.cpp | 1021 for (const MachineBasicBlock::RegisterMaskPair &RegMask : ExitBB->liveins()) { in ValidateLiveOuts() local
1024 if (RegMask.PhysReg == ARM::VPR) { in ValidateLiveOuts()
1030 if (QPRs->contains(RegMask.PhysReg)) in ValidateLiveOuts()
1031 if (auto *MI = RDA.getLocalLiveOutMIDef(Header, RegMask.PhysReg)) in ValidateLiveOuts()
|