| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | RegUsageInfoPropagate.cpp | 53 static void setRegMask(MachineInstr &MI, ArrayRef<uint32_t> RegMask) { in setRegMask() argument
54 assert(RegMask.size() == in setRegMask()
61 MO.setRegMask(RegMask.data()); in setRegMask()
151 const ArrayRef<uint32_t> RegMask = PRUI->getRegUsageInfo(F); in run() local
152 if (RegMask.empty()) in run()
154 setRegMask(MI, RegMask); in run()
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| H A D | RegUsageInfoCollector.cpp | 147 std::vector<uint32_t> RegMask; in run() local
153 RegMask.resize(RegMaskSize, ~((uint32_t)0)); in run()
165 auto SetRegAsDefined = [&RegMask](MCRegister Reg) { in run()
166 RegMask[Reg.id() / 32] &= ~(1u << Reg.id() % 32); in run()
209 if (MachineOperand::clobbersPhysReg(&(RegMask[0]), PReg)) in run()
216 PRUI.storeUpdateRegUsageInfo(F, RegMask); in run()
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| H A D | LiveRegUnits.cpp | 22 void LiveRegUnits::removeRegsNotPreserved(const uint32_t *RegMask) { in removeRegsNotPreserved() argument
25 if (MachineOperand::clobbersPhysReg(RegMask, *RootReg)) { in removeRegsNotPreserved()
33 void LiveRegUnits::addRegsInMask(const uint32_t *RegMask) { in addRegsInMask() argument
36 if (MachineOperand::clobbersPhysReg(RegMask, *RootReg)) { in addRegsInMask()
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| H A D | RegisterUsageInfo.cpp | 60 const Function &FP, ArrayRef<uint32_t> RegMask) { in storeUpdateRegUsageInfo() argument
61 RegMasks[&FP] = RegMask; in storeUpdateRegUsageInfo()
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| H A D | MachineStableHash.cpp | 139 const uint32_t *RegMask = MO.getRegMask(); in stableHashValue() local
140 std::vector<llvm::stable_hash> RegMaskHashes(RegMask, in stableHashValue()
141 RegMask + RegMaskSize); in stableHashValue()
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| H A D | MachineOperand.cpp | 366 const uint32_t *RegMask = getRegMask(); in isIdenticalTo() local
368 if (RegMask == OtherRegMask) in isIdenticalTo()
375 return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask); in isIdenticalTo()
437 const uint32_t *RegMask = MO.getRegMask(); in hash_value() local
438 std::vector<stable_hash> RegMaskHashes(RegMask, RegMask + RegMaskSize); in hash_value()
974 const uint32_t *RegMask = getRegLiveOut(); in print() local
981 if (RegMask[Reg / 32] & (1U << (Reg % 32))) { in print()
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| H A D | MachineCopyPropagation.cpp | 130 const uint32_t *RegMask = RegMaskOp.getRegMask(); in getPreservedRegUnits() local
131 auto [It, Inserted] = RegMaskToPreservedRegUnits.try_emplace(RegMask); in getPreservedRegUnits()
950 const MachineOperand *RegMask = nullptr; in ForwardCopyPropagateBlock() local
953 RegMask = &MO; in ForwardCopyPropagateBlock()
976 if (RegMask) { in ForwardCopyPropagateBlock()
978 Tracker.getPreservedRegUnits(*RegMask, *TRI); in ForwardCopyPropagateBlock()
990 if (!RegMask->clobbersPhysReg(Reg)) { in ForwardCopyPropagateBlock()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/AsmParser/ |
| H A D | M68kAsmParser.cpp | 84 RegMask, enumerator
112 uint16_t RegMask; member
278 case Kind::RegMask: in print()
279 OS << "RegMask(" << format("%04x", RegMask) << ")"; in print()
387 if (MemOp.Op == M68kMemOp::Kind::RegMask) in isMoveMask()
402 uint16_t MoveMask = MemOp.RegMask; in addMoveMaskOperands()
898 M68kMemOp MemOp(M68kMemOp::Kind::RegMask); in parseRegOrMoveMask()
899 MemOp.RegMask = 0; in parseRegOrMoveMask()
903 (MemOp.Op == M68kMemOp::Kind::RegMask) && (MemOp.RegMask == 0); in parseRegOrMoveMask()
934 MemOp.Op = M68kMemOp::Kind::RegMask; in parseRegOrMoveMask()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUCallingConv.td | 175 // Trivial class to denote when a def is used only to get a RegMask, i.e.
178 class RegMask<dag mask> : CalleeSavedRegs<mask>;
180 def AMDGPU_AllVGPRs : RegMask<
184 def AMDGPU_AllAGPRs : RegMask<
188 def AMDGPU_AllVectorRegs : RegMask<
192 def AMDGPU_AllAllocatableSRegs : RegMask<
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| H A D | SILowerSGPRSpills.cpp | 65 void determineRegsForWWMAllocation(MachineFunction &MF, BitVector &RegMask);
347 BitVector &RegMask) { in determineRegsForWWMAllocation() argument
370 TRI->markSuperRegs(RegMask, Reg); in determineRegsForWWMAllocation()
377 TRI->markSuperRegs(RegMask, AMDGPU::VGPR0); in determineRegsForWWMAllocation()
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| H A D | GCNRegPressure.cpp | 855 LaneBitmask RegMask = MRI.getMaxLaneMaskForVReg(Reg); in getRegLiveThroughMask() local
856 if ((RegMask & Mask) == RegMask && IsInOneSegment(LI)) in getRegLiveThroughMask()
857 LiveThroughMask = RegMask; in getRegLiveThroughMask()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MachineOperand.h | 174 const uint32_t *RegMask; // For MO_RegisterMask and MO_RegisterLiveOut. member
646 static bool clobbersPhysReg(const uint32_t *RegMask, MCRegister PhysReg) { in clobbersPhysReg() argument
650 return !(RegMask[PhysReg.id() / 32] & (1u << PhysReg.id() % 32)); in clobbersPhysReg()
662 return Contents.RegMask; in getRegMask()
673 return Contents.RegMask; in getRegLiveOut()
739 Contents.RegMask = RegMaskPtr; in setRegMask()
940 Op.Contents.RegMask = Mask; in CreateRegMask()
946 Op.Contents.RegMask = Mask; in CreateRegLiveOut()
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| H A D | LiveRegUnits.h | 110 LLVM_ABI void removeRegsNotPreserved(const uint32_t *RegMask);
114 LLVM_ABI void addRegsInMask(const uint32_t *RegMask);
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| H A D | RegisterUsageInfo.h | 46 ArrayRef<uint32_t> RegMask);
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64CollectLOH.cpp | 493 static void handleRegMaskClobber(const uint32_t *RegMask, MCPhysReg Reg, in handleRegMaskClobber() argument
495 if (!MachineOperand::clobbersPhysReg(RegMask, Reg)) in handleRegMaskClobber()
506 const uint32_t *RegMask = MO.getRegMask(); in handleNormalInst() local
508 handleRegMaskClobber(RegMask, Reg, LOHInfos); in handleNormalInst()
510 handleRegMaskClobber(RegMask, Reg, LOHInfos); in handleNormalInst()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFISelLowering.cpp | 421 static void resetRegMaskBit(const TargetRegisterInfo *TRI, uint32_t *RegMask, in resetRegMaskBit() argument
424 RegMask[SubReg / 32] &= ~(1u << (SubReg % 32)); in resetRegMaskBit()
430 uint32_t *RegMask = MF.allocateRegMask(); in regMaskFromTemplate() local
432 memcpy(RegMask, BaseRegMask, sizeof(RegMask[0]) * RegMaskSize); in regMaskFromTemplate()
433 return RegMask; in regMaskFromTemplate()
553 uint32_t *RegMask = regMaskFromTemplate( in LowerCall() local
556 resetRegMaskBit(TRI, RegMask, RegPair.first); in LowerCall()
558 resetRegMaskBit(TRI, RegMask, BPF::R0); in LowerCall()
559 Ops.push_back(DAG.getRegisterMask(RegMask)); in LowerCall()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kRegisterInfo.cpp | 153 const uint32_t *RegMask = getCallPreservedMask(MF, CC); in getReservedRegs() local
154 if (MachineOperand::clobbersPhysReg(RegMask, getBaseRegister())) in getReservedRegs()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/ExecutionEngine/JITLink/ |
| H A D | aarch32.h | 226 static constexpr uint32_t RegMask = 0x0000f000;
254 static constexpr HalfWords RegMask{0x0000, 0x0f00};
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVTargetTransformInfo.cpp | 449 [&](ArrayRef<int> RegMask, unsigned SrcReg, unsigned DestReg) { in costShuffleViaSplitting() argument
450 if (ShuffleVectorInst::isIdentityMask(RegMask, RegMask.size())) in costShuffleViaSplitting()
452 if (!ReusedSingleSrcShuffles.insert(std::make_pair(RegMask, SrcReg)) in costShuffleViaSplitting()
457 FixedVectorType::get(SingleOpTy->getElementType(), RegMask.size()), in costShuffleViaSplitting()
458 SingleOpTy, RegMask, CostKind, 0, nullptr); in costShuffleViaSplitting()
460 [&](ArrayRef<int> RegMask, unsigned Idx1, unsigned Idx2, bool NewReg) { in costShuffleViaSplitting() argument
463 FixedVectorType::get(SingleOpTy->getElementType(), RegMask.size()), in costShuffleViaSplitting()
464 SingleOpTy, RegMask, CostKind, 0, nullptr); in costShuffleViaSplitting()
525 [&](ArrayRef<int> RegMask, unsigned SrcReg, unsigned DestReg) { in costShuffleViaVRegSplitting() argument
526 if (ShuffleVectorInst::isIdentityMask(RegMask, RegMask.size())) in costShuffleViaVRegSplitting()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/ExecutionEngine/JITLink/ |
| H A D | aarch32.cpp | 345 uint16_t Hi = R.Hi & FixupInfo<Kind>::RegMask.Hi; in checkRegister()
346 uint16_t Lo = R.Lo & FixupInfo<Kind>::RegMask.Lo; in checkRegister()
352 uint32_t Wd = R.Wd & FixupInfo<Kind>::RegMask; in checkRegister()
358 static constexpr HalfWords Mask = FixupInfo<Kind>::RegMask; in writeRegister()
367 static constexpr uint32_t Mask = FixupInfo<Kind>::RegMask; in writeRegister()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZElimCompare.cpp | 635 const uint32_t *RegMask; in fuseCompareOperations() local
637 RegMask = MBBI->getOperand(3).getRegMask(); in fuseCompareOperations()
675 MIB.addRegMask(RegMask); in fuseCompareOperations()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCCodeEmitter.cpp | 639 unsigned RegMask = MI.getOperand(OpIdx).getImm(); in EncodeMatrixTileListRegisterClass() local
640 assert(RegMask <= 0xFF && "Invalid register mask!"); in EncodeMatrixTileListRegisterClass()
641 return RegMask; in EncodeMatrixTileListRegisterClass()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLoweringCall.cpp | 1124 uint32_t *RegMask) const { in LowerCallResult()
1141 if (RegMask) { in LowerCallResult()
1143 RegMask[SubReg / 32] &= ~(1u << (SubReg % 32)); in LowerCallResult()
2520 uint32_t *RegMask = nullptr; in LowerCall() local
2531 RegMask = MF.allocateRegMask(); in LowerCall()
2533 memcpy(RegMask, Mask, sizeof(RegMask[0]) * RegMaskSize); in LowerCall()
2540 RegMask[SubReg / 32] &= ~(1u << (SubReg % 32)); in LowerCall()
2544 Ops.push_back(DAG.getRegisterMask(RegMask)); in LowerCall()
2638 InVals, RegMask); in LowerCall()
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| /freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | VectorUtils.cpp | 754 SmallVectorImpl<int> &RegMask = Dest[I]; in processShuffleMasks() local
755 if (RegMask.empty()) in processShuffleMasks()
760 FirstMask = RegMask; in processShuffleMasks()
764 SecondMask = RegMask; in processShuffleMasks()
769 RegMask.clear(); in processShuffleMasks()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ScheduleDAGRRList.cpp | 1321 static void CheckForLiveRegDefMasked(SUnit *SU, const uint32_t *RegMask, in CheckForLiveRegDefMasked() argument
1329 if (!MachineOperand::clobbersPhysReg(RegMask, i)) continue; in CheckForLiveRegDefMasked()
1417 if (const uint32_t *RegMask = getNodeRegMask(Node)) in DelayForLiveRegsBottomUp() local
1418 CheckForLiveRegDefMasked(SU, RegMask, in DelayForLiveRegsBottomUp()
2862 const uint32_t *RegMask = getNodeRegMask(SU->getNode()); in canClobberReachingPhysRegUse() local
2863 if (ImpDefs.empty() && !RegMask) in canClobberReachingPhysRegUse()
2872 if (RegMask && in canClobberReachingPhysRegUse()
2873 MachineOperand::clobbersPhysReg(RegMask, SuccPred.getReg()) && in canClobberReachingPhysRegUse()
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