| /freebsd/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCRegisterInfo.h | 468 bool isSubRegister(MCRegister RegA, MCRegister RegB) const { in isSubRegister() argument
469 return isSuperRegister(RegB, RegA); in isSubRegister()
473 bool isSuperRegister(MCRegister RegA, MCRegister RegB) const;
476 bool isSubRegisterEq(MCRegister RegA, MCRegister RegB) const { in isSubRegisterEq() argument
477 return isSuperRegisterEq(RegB, RegA); in isSubRegisterEq()
482 bool isSuperRegisterEq(MCRegister RegA, MCRegister RegB) const { in isSuperRegisterEq() argument
483 return RegA == RegB || isSuperRegister(RegA, RegB); in isSuperRegisterEq()
488 bool isSuperOrSubRegisterEq(MCRegister RegA, MCRegister RegB) const { in isSuperOrSubRegisterEq() argument
489 return isSubRegisterEq(RegA, RegB) || isSuperRegister(RegA, RegB); in isSuperOrSubRegisterEq()
493 bool regsOverlap(MCRegister RegA, MCRegister RegB) const;
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TwoAddressInstructionPass.cpp | 141 bool regsAreCompatible(Register RegA, Register RegB) const;
150 bool isProfitableToCommute(Register RegA, Register RegB, Register RegC,
156 bool isProfitableToConv3Addr(Register RegA, Register RegB);
159 MachineBasicBlock::iterator &nmi, Register RegA,
544 bool TwoAddressInstructionImpl::regsAreCompatible(Register RegA, in regsAreCompatible() argument
546 if (RegA == RegB) in regsAreCompatible()
548 if (!RegA || !RegB) in regsAreCompatible()
550 return TRI->regsOverlap(RegA, RegB); in regsAreCompatible()
633 bool TwoAddressInstructionImpl::isProfitableToCommute(Register RegA, in isProfitableToCommute() argument
672 MCRegister ToRegA = getMappedReg(RegA, DstRegMap); in isProfitableToCommute()
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| H A D | ImplicitNullChecks.cpp | 286 Register RegA = MOA.getReg(); in canReorder() local
293 if (TRI->regsOverlap(RegA, RegB) && (MOA.isDef() || MOB.isDef())) in canReorder()
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| H A D | TargetInstrInfo.cpp | 1099 Register RegA = OpA.getReg(); in reassociateOps() local
1105 if (RegA.isVirtual()) in reassociateOps()
1106 MRI.constrainRegClass(RegA, RC); in reassociateOps()
1193 std::swap(RegA, NewVR); in reassociateOps()
1205 MIB2 = MIB2.addReg(RegA, getKillRegState(KillA)); in reassociateOps()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86DynAllocaExpander.cpp | 224 unsigned RegA = Is64Bit ? X86::RAX : X86::EAX; in lower() local
226 .addReg(RegA, RegState::Undef); in lower()
238 unsigned RegA = Is64Bit ? X86::RAX : X86::EAX; in lower() local
240 .addReg(RegA, RegState::Undef); in lower()
251 unsigned RegA = Is64BitAlloca ? X86::RAX : X86::EAX; in lower() local
252 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::COPY), RegA) in lower()
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| H A D | X86RegisterInfo.cpp | 674 auto IsSubReg = [&](MCRegister RegA, MCRegister RegB) { in isArgumentRegister() argument
675 return TRI.isSuperOrSubRegisterEq(RegA, RegB); in isArgumentRegister()
681 [&](MCRegister &RegA) { return IsSubReg(RegA, Reg); }) || in isArgumentRegister() argument
691 [&](MCRegister &RegA) { return IsSubReg(RegA, Reg); })) in isArgumentRegister() argument
696 [&](MCRegister &RegA) { return IsSubReg(RegA, Reg); })) in isArgumentRegister() argument
703 [&](MCRegister &RegA) { return IsSubReg(RegA, Reg); })) in isArgumentRegister() argument
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| /freebsd/contrib/llvm-project/llvm/lib/MC/ |
| H A D | MCRegisterInfo.cpp | 207 bool MCRegisterInfo::regsOverlap(MCRegister RegA, MCRegister RegB) const { in regsOverlap() argument
209 auto RangeA = regunits(RegA); in regsOverlap()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 449 bool regsOverlap(Register RegA, Register RegB) const { in regsOverlap() argument
450 if (RegA == RegB) in regsOverlap()
452 if (RegA.isPhysical() && RegB.isPhysical()) in regsOverlap()
453 return MCRegisterInfo::regsOverlap(RegA.asMCReg(), RegB.asMCReg()); in regsOverlap()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 2224 for (auto &RegA : DefsA) in isDependent() local
2227 if (RegA == RegB) in isDependent()
2230 if (RegA.isPhysical() && llvm::is_contained(HRI.subregs(RegA), RegB)) in isDependent()
2233 if (RegB.isPhysical() && llvm::is_contained(HRI.subregs(RegB), RegA)) in isDependent()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 510 Register RegA = Prev->getOperand(AddOpIdx).getReg(); in getFMAPatterns() local
511 MachineInstr *Leaf = MRI->getUniqueVRegDef(RegA); in getFMAPatterns()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 6938 Register RegA = Root.getOperand(1).getReg(); in genSubAdd2SubSub() local
6944 Register NewVR = MRI.createVirtualRegister(MRI.getRegClass(RegA)); in genSubAdd2SubSub()
6961 .addReg(RegA, getKillRegState(RegAIsKill)) in genSubAdd2SubSub()
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