| /freebsd/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCRegisterInfo.h | 484 bool isSubRegister(MCRegister RegA, MCRegister RegB) const { in isSubRegister() argument
485 return isSuperRegister(RegB, RegA); in isSubRegister()
489 bool isSuperRegister(MCRegister RegA, MCRegister RegB) const;
492 bool isSubRegisterEq(MCRegister RegA, MCRegister RegB) const { in isSubRegisterEq() argument
493 return isSuperRegisterEq(RegB, RegA); in isSubRegisterEq()
498 bool isSuperRegisterEq(MCRegister RegA, MCRegister RegB) const { in isSuperRegisterEq() argument
499 return RegA == RegB || isSuperRegister(RegA, RegB); in isSuperRegisterEq()
504 bool isSuperOrSubRegisterEq(MCRegister RegA, MCRegister RegB) const { in isSuperOrSubRegisterEq() argument
505 return isSubRegisterEq(RegA, RegB) || isSuperRegister(RegA, RegB); in isSuperOrSubRegisterEq()
509 bool regsOverlap(MCRegister RegA, MCRegister RegB) const;
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TwoAddressInstructionPass.cpp | 141 bool regsAreCompatible(Register RegA, Register RegB) const;
150 bool isProfitableToCommute(Register RegA, Register RegB, Register RegC,
156 bool isProfitableToConv3Addr(Register RegA, Register RegB);
159 MachineBasicBlock::iterator &nmi, Register RegA,
547 bool TwoAddressInstructionImpl::regsAreCompatible(Register RegA, in regsAreCompatible() argument
549 if (RegA == RegB) in regsAreCompatible()
551 if (!RegA || !RegB) in regsAreCompatible()
553 return TRI->regsOverlap(RegA, RegB); in regsAreCompatible()
636 bool TwoAddressInstructionImpl::isProfitableToCommute(Register RegA, in isProfitableToCommute() argument
675 MCRegister ToRegA = getMappedReg(RegA, DstRegMap); in isProfitableToCommute()
[all …]
|
| H A D | ImplicitNullChecks.cpp | 285 Register RegA = MOA.getReg(); in canReorder() local
292 if (TRI->regsOverlap(RegA, RegB) && (MOA.isDef() || MOB.isDef())) in canReorder()
|
| H A D | TargetInstrInfo.cpp | 1331 Register RegA = OpA.getReg(); in reassociateOps() local
1337 if (RegA.isVirtual()) in reassociateOps()
1338 MRI.constrainRegClass(RegA, RC); in reassociateOps()
1425 std::swap(RegA, NewVR); in reassociateOps()
1437 MIB2 = MIB2.addReg(RegA, getKillRegState(KillA)); in reassociateOps()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86DynAllocaExpander.cpp | 227 unsigned RegA = Is64Bit ? X86::RAX : X86::EAX; in lower() local
229 .addReg(RegA, RegState::Undef); in lower()
241 unsigned RegA = Is64Bit ? X86::RAX : X86::EAX; in lower() local
243 .addReg(RegA, RegState::Undef); in lower()
254 unsigned RegA = Is64BitAlloca ? X86::RAX : X86::EAX; in lower() local
255 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::COPY), RegA) in lower()
|
| H A D | X86RegisterInfo.cpp | 686 auto IsSubReg = [&](MCRegister RegA, MCRegister RegB) { in isArgumentRegister() argument
687 return TRI.isSuperOrSubRegisterEq(RegA, RegB); in isArgumentRegister()
693 [&](MCRegister &RegA) { return IsSubReg(RegA, Reg); }) || in isArgumentRegister() argument
703 [&](MCRegister &RegA) { return IsSubReg(RegA, Reg); })) in isArgumentRegister() argument
708 [&](MCRegister &RegA) { return IsSubReg(RegA, Reg); })) in isArgumentRegister() argument
715 [&](MCRegister &RegA) { return IsSubReg(RegA, Reg); })) in isArgumentRegister() argument
|
| /freebsd/contrib/llvm-project/llvm/lib/MC/ |
| H A D | MCRegisterInfo.cpp | 211 bool MCRegisterInfo::regsOverlap(MCRegister RegA, MCRegister RegB) const { in regsOverlap() argument
213 auto RangeA = regunits(RegA); in regsOverlap()
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 462 bool regsOverlap(Register RegA, Register RegB) const { in regsOverlap() argument
463 if (RegA == RegB) in regsOverlap()
465 if (RegA.isPhysical() && RegB.isPhysical()) in regsOverlap()
466 return MCRegisterInfo::regsOverlap(RegA.asMCReg(), RegB.asMCReg()); in regsOverlap()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 2227 for (auto &RegA : DefsA) in isDependent() local
2230 if (RegA == RegB) in isDependent()
2233 if (RegA.isPhysical() && llvm::is_contained(HRI.subregs(RegA), RegB)) in isDependent()
2236 if (RegB.isPhysical() && llvm::is_contained(HRI.subregs(RegB), RegA)) in isDependent()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 508 Register RegA = Prev->getOperand(AddOpIdx).getReg(); in getFMAPatterns() local
509 MachineInstr *Leaf = MRI->getUniqueVRegDef(RegA); in getFMAPatterns()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 7733 Register RegA = Root.getOperand(1).getReg(); in genSubAdd2SubSub() local
7757 .addReg(RegA, getKillRegState(RegAIsKill)) in genSubAdd2SubSub()
|