141   bool regsAreCompatible(Register RegA, Register RegB) const;
150   bool isProfitableToCommute(Register RegA, Register RegB, Register RegC,
156   bool isProfitableToConv3Addr(Register RegA, Register RegB);
159                           MachineBasicBlock::iterator &nmi, Register RegA,
544 bool TwoAddressInstructionImpl::regsAreCompatible(Register RegA,  in regsAreCompatible()  argument
546   if (RegA == RegB)  in regsAreCompatible()
548   if (!RegA || !RegB)  in regsAreCompatible()
550   return TRI->regsOverlap(RegA, RegB);  in regsAreCompatible()
633 bool TwoAddressInstructionImpl::isProfitableToCommute(Register RegA,  in isProfitableToCommute()  argument
672   MCRegister ToRegA = getMappedReg(RegA, DstRegMap);  in isProfitableToCommute()
720   if (isRevCopyChain(RegC, RegA, MaxDataFlowEdge))  in isProfitableToCommute()
723   if (isRevCopyChain(RegB, RegA, MaxDataFlowEdge))  in isProfitableToCommute()
760     Register RegA = MI->getOperand(DstIdx).getReg();  in commuteInstruction()  local
761     SrcRegMap[RegA] = FromRegC;  in commuteInstruction()
769 bool TwoAddressInstructionImpl::isProfitableToConv3Addr(Register RegA,  in isProfitableToConv3Addr()  argument
780   MCRegister ToRegA = getMappedReg(RegA, DstRegMap);  in isProfitableToConv3Addr()
788     Register RegA, Register RegB, unsigned &Dist) {  in convertInstTo3Addr()  argument
821   SrcRegMap.erase(RegA);  in convertInstTo3Addr()
1571     Register RegA = DstMO.getReg();  in processTiedPairs()  local
1578     if (RegA == RegB) {  in processTiedPairs()
1585     LastCopiedReg = RegA;  in processTiedPairs()
1596              MI->getOperand(i).getReg() != RegA);  in processTiedPairs()
1601                                       TII->get(TargetOpcode::COPY), RegA);  in processTiedPairs()
1607       if (RegA.isVirtual()) {  in processTiedPairs()
1608         assert(TRI->getMatchingSuperRegClass(RC, MRI->getRegClass(RegA),  in processTiedPairs()
1614         assert(TRI->getMatchingSuperReg(RegA, SubRegB, MRI->getRegClass(RegB))  in processTiedPairs()
1630       if (RegA.isVirtual()) {  in processTiedPairs()
1631         LiveInterval &LI = LIS->getInterval(RegA);  in processTiedPairs()
1639         for (MCRegUnit Unit : TRI->regunits(RegA)) {  in processTiedPairs()
1660     if (RegA.isVirtual() && RegB.isVirtual())  in processTiedPairs()
1661       MRI->constrainRegClass(RegA, RC);  in processTiedPairs()
1662     MO.setReg(RegA);  in processTiedPairs()
1756     Register RegA = DstMO.getReg();  in processStatepoint()  local
1760     if (RegA == RegB)  in processStatepoint()
1770       const auto &DefLI = LIS->getInterval(RegA);  in processStatepoint()
1787     if (!MRI->constrainRegClass(RegB, MRI->getRegClass(RegA))) {  in processStatepoint()
1789                         << " to register class of " << printReg(RegA, TRI, 0)  in processStatepoint()
1794     MRI->replaceRegWith(RegA, RegB);  in processStatepoint()
1799       LiveInterval &Other = LIS->getInterval(RegA);  in processStatepoint()
1810       LIS->removeInterval(RegA);  in processStatepoint()
1817       LiveVariables::VarInfo &DstInfo = LV->getVarInfo(RegA);  in processStatepoint()