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Searched refs:Reg0 (Results 1 – 25 of 26) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsTargetStreamer.h128 void emitR(unsigned Opcode, MCRegister Reg0, SMLoc IDLoc,
132 void emitRX(unsigned Opcode, MCRegister Reg0, MCOperand Op1, SMLoc IDLoc,
134 void emitRI(unsigned Opcode, MCRegister Reg0, int32_t Imm, SMLoc IDLoc,
136 void emitRR(unsigned Opcode, MCRegister Reg0, MCRegister Reg1, SMLoc IDLoc,
138 void emitRRX(unsigned Opcode, MCRegister Reg0, MCRegister Reg1, MCOperand Op2,
140 void emitRRR(unsigned Opcode, MCRegister Reg0, MCRegister Reg1,
142 void emitRRRX(unsigned Opcode, MCRegister Reg0, MCRegister Reg1,
145 void emitRRI(unsigned Opcode, MCRegister Reg0, MCRegister Reg1, int16_t Imm,
147 void emitRRIII(unsigned Opcode, MCRegister Reg0, MCRegister Reg1,
H A DMipsTargetStreamer.cpp185 void MipsTargetStreamer::emitR(unsigned Opcode, MCRegister Reg0, SMLoc IDLoc, in emitR() argument
189 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitR()
194 void MipsTargetStreamer::emitRX(unsigned Opcode, MCRegister Reg0, MCOperand Op1, in emitRX() argument
198 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRX()
204 void MipsTargetStreamer::emitRI(unsigned Opcode, MCRegister Reg0, int32_t Imm, in emitRI() argument
206 emitRX(Opcode, Reg0, MCOperand::createImm(Imm), IDLoc, STI); in emitRI()
209 void MipsTargetStreamer::emitRR(unsigned Opcode, MCRegister Reg0, in emitRR() argument
212 emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI); in emitRR()
225 void MipsTargetStreamer::emitRRX(unsigned Opcode, MCRegister Reg0, in emitRRX() argument
230 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRRX()
[all …]
H A DMipsMCCodeEmitter.cpp122 unsigned Reg0 = Ctx.getRegisterInfo()->getEncodingValue(RegOp0); in LowerCompactBranch() local
127 assert(Reg0 != Reg1 && "Instruction has bad operands ($rs == $rt)!"); in LowerCompactBranch()
128 if (Reg0 < Reg1) in LowerCompactBranch()
131 if (Reg0 >= Reg1) in LowerCompactBranch()
135 if (Reg1 >= Reg0) in LowerCompactBranch()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FixupSetCC.cpp89 Register Reg0 = MI.getOperand(0).getReg(); in runOnMachineFunction() local
90 for (auto &Use : MRI->use_instructions(Reg0)) in runOnMachineFunction()
137 .addReg(Reg0) in runOnMachineFunction()
H A DX86CompressEVEX.cpp193 Register Reg0 = MI.getOperand(0).getReg(); in CompressEVEXImpl() local
199 if (Reg1 == Reg0) in CompressEVEXImpl()
204 !MI.getOperand(2).isReg() || MI.getOperand(2).getReg() != Reg0) in CompressEVEXImpl()
H A DX86ExpandPseudo.cpp479 Register Reg0 = TRI->getSubReg(Reg, X86::sub_mask_0); in expandMI() local
484 .addReg(Reg0, RegState::Define | getDeadRegState(DstIsDead)); in expandMI()
515 Register Reg0 = TRI->getSubReg(Reg, X86::sub_mask_0); in expandMI() local
530 MIBLo.addReg(Reg0, getKillRegState(SrcIsKill)); in expandMI()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonPeephole.cpp222 Register Reg0 = Op0.getReg(); in runOnMachineFunction() local
223 const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0); in runOnMachineFunction()
227 if (Reg0.isVirtual()) { in runOnMachineFunction()
229 if (unsigned PeepholeSrc = PeepholeMap.lookup(Reg0)) { in runOnMachineFunction()
H A DHexagonBitTracker.cpp306 unsigned Reg0 = Reg[0].Reg; in evaluate() local
837 return rr0(eSXT(RegisterCell::self(0, W0).regify(Reg0), 8), Outputs); in evaluate()
839 return rr0(eSXT(RegisterCell::self(0, W0).regify(Reg0), 16), Outputs); in evaluate()
841 return rr0(eZXT(RegisterCell::self(0, W0).regify(Reg0), 8), Outputs); in evaluate()
843 return rr0(eZXT(RegisterCell::self(0, W0).regify(Reg0), 16), Outputs); in evaluate()
/freebsd/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCRegisterInfo.h716 uint16_t Reg0 = 0; variable
724 Reg0 = MCRI->RegUnitRoots[RegUnit][0]; in MCRegUnitRootIterator()
730 return Reg0;
735 return Reg0; in isValid()
741 Reg0 = Reg1;
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp2164 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVLD() local
2186 Ops.push_back(Reg0); in SelectVLD()
2189 Ops.push_back(Reg0); in SelectVLD()
2202 const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain }; in SelectVLD()
2215 Ops.push_back(Reg0); in SelectVLD()
2219 Ops.push_back(Reg0); in SelectVLD()
2299 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVST() local
2346 Ops.push_back(Reg0); in SelectVST()
2350 Ops.push_back(Reg0); in SelectVST()
2375 const SDValue OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain }; in SelectVST()
[all …]
H A DThumb2SizeReduction.cpp751 Register Reg0 = MI->getOperand(0).getReg(); in ReduceTo2Addr() local
760 if (!isARMLowRegister(Reg0) || !isARMLowRegister(Reg1) in ReduceTo2Addr()
763 if (Reg0 != Reg2) { in ReduceTo2Addr()
766 if (Reg1 != Reg0) in ReduceTo2Addr()
773 } else if (Reg0 != Reg1) { in ReduceTo2Addr()
778 MI->getOperand(CommOpIdx2).getReg() != Reg0) in ReduceTo2Addr()
785 if (Entry.LowRegs2 && !isARMLowRegister(Reg0)) in ReduceTo2Addr()
H A DARMAsmPrinter.cpp339 Register Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0); in PrintAsmOperand() local
340 O << ARMInstPrinter::getRegisterName(Reg0) << ", "; in PrintAsmOperand()
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp232 Register Reg0 = cast<RegisterSDNode>(V0)->getReg(); in tryInlineAsm() local
254 SDValue T0 = CurDAG->getCopyToReg(Sub0, dl, Reg0, Sub0, in tryInlineAsm()
268 SDValue T0 = CurDAG->getCopyFromReg(Chain, dl, Reg0, MVT::i32, in tryInlineAsm()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEFrameLowering.cpp453 MCRegister Reg0 = RegInfo.getSubReg(Reg, Mips::sub_lo); in emitPrologue() local
457 std::swap(Reg0, Reg1); in emitPrologue()
459 CFIBuilder.buildOffset(Reg0, Offset); in emitPrologue()
462 MCRegister Reg0 = Reg; in emitPrologue() local
466 std::swap(Reg0, Reg1); in emitPrologue()
468 CFIBuilder.buildOffset(Reg0, Offset); in emitPrologue()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelDAGToDAG.cpp200 unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg(); in selectInlineAsm() local
223 CurDAG->getCopyToReg(Sub0, dl, Reg0, Sub0, RegCopy.getValue(1)); in selectInlineAsm()
237 CurDAG->getCopyFromReg(Chain, dl, Reg0, MVT::i32, Chain.getValue(1)); in selectInlineAsm()
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVLegalizerInfo.cpp364 Register Reg0 = Op0.getReg(); in legalizeCustom() local
370 MRI.getType(Reg0).isPointer() && MRI.getType(Reg1).isPointer()) { in legalizeCustom()
376 Op0.setReg(convertPtrToInt(Reg0, ConvT, SpirvTy, Helper, MRI, GR)); in legalizeCustom()
H A DSPIRVInstructionSelector.cpp3656 Register Reg0; in selectFirstBitSet64() local
3664 Reg0 = GR.getOrCreateConstInt(0, I, ResType, TII, ZeroAsNull); in selectFirstBitSet64()
3673 Reg0 = GR.getOrCreateConstVector(0, I, ResType, TII, ZeroAsNull); in selectFirstBitSet64()
3682 Register SecondaryShiftReg = Reg0; in selectFirstBitSet64()
3689 PrimaryShiftReg = Reg0; in selectFirstBitSet64()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineInstr.cpp2644 Register Reg0 = getOperand(0).getReg(); in getFirst2RegLLTs() local
2646 return std::tuple(Reg0, getRegInfo()->getType(Reg0), Reg1, in getFirst2RegLLTs()
2652 Register Reg0 = getOperand(0).getReg(); in getFirst3RegLLTs() local
2655 return std::tuple(Reg0, getRegInfo()->getType(Reg0), Reg1, in getFirst3RegLLTs()
2662 Register Reg0 = getOperand(0).getReg(); in getFirst4RegLLTs() local
2667 Reg0, getRegInfo()->getType(Reg0), Reg1, getRegInfo()->getType(Reg1), in getFirst4RegLLTs()
2674 Register Reg0 = getOperand(0).getReg(); in getFirst5RegLLTs() local
2680 Reg0, getRegInfo()->getType(Reg0), Reg1, getRegInfo()->getType(Reg1), in getFirst5RegLLTs()
H A DTargetInstrInfo.cpp199 Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register(); in commuteInstructionImpl() local
228 if ((ImplReg.isVirtual() && ImplReg == Reg0) || in commuteInstructionImpl()
229 (ImplReg.isPhysical() && Reg0.isPhysical() && in commuteInstructionImpl()
230 TRI->isSubRegisterEq(ImplReg, Reg0))) in commuteInstructionImpl()
237 if (HasDef && Reg0 == Reg1 && in commuteInstructionImpl()
240 Reg0 = Reg2; in commuteInstructionImpl()
242 } else if (HasDef && Reg0 == Reg2 && in commuteInstructionImpl()
245 Reg0 = Reg1; in commuteInstructionImpl()
259 CommutedMI->getOperand(0).setReg(Reg0); in commuteInstructionImpl()
262 CommutedMI->getOperand(Idx).setReg(Reg0); in commuteInstructionImpl()
H A DRegisterCoalescer.cpp2780 Register Reg0; in valuesIdentical() local
2781 std::tie(Orig0, Reg0) = followCopyChain(Value0); in valuesIdentical()
2782 if (Orig0 == Value1 && Reg0 == Other.Reg) in valuesIdentical()
2792 return Orig0 == Orig1 && Reg0 == Reg1; in valuesIdentical()
2798 return Orig0->def == Orig1->def && Reg0 == Reg1; in valuesIdentical()
H A DRegAllocFast.cpp1404 Register Reg0 = MO0.getReg(); in findAndSortDefOperandIndexes() local
1406 const TargetRegisterClass &RC0 = *MRI->getRegClass(Reg0); in findAndSortDefOperandIndexes()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMInstPrinter.cpp1492 MCRegister Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwo() local
1495 printRegName(O, Reg0); in printVectorListTwo()
1505 MCRegister Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoSpaced() local
1508 printRegName(O, Reg0); in printVectorListTwoSpaced()
1560 MCRegister Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoAllLanes() local
1563 printRegName(O, Reg0); in printVectorListTwoAllLanes()
1607 MCRegister Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoSpacedAllLanes() local
1610 printRegName(O, Reg0); in printVectorListTwoSpacedAllLanes()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FrameLowering.cpp1295 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg()); in InsertSEH() local
1297 .addImm(Reg0) in InsertSEH()
1304 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg()); in InsertSEH() local
1306 .addImm(Reg0) in InsertSEH()
1315 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg()); in InsertSEH() local
1318 .addImm(Reg0) in InsertSEH()
1328 Register Reg0 = MBBI->getOperand(1).getReg(); in InsertSEH() local
1330 if (Reg0 == AArch64::FP && Reg1 == AArch64::LR) in InsertSEH()
1336 .addImm(RegInfo->getSEHRegNum(Reg0)) in InsertSEH()
1366 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg()); in InsertSEH() local
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp2273 Register Reg0 = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass); in loadImmediate() local
2275 BuildMI(MBB, MBBI, DL, get(SystemZ::IMPLICIT_DEF), Reg0); in loadImmediate()
2277 .addReg(Reg0).addImm(Value >> 32); in loadImmediate()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp1156 Register Reg0 = MI.getOperand(0).getReg(); in commuteInstructionImpl() local
1166 if (Reg0 == Reg1) { in commuteInstructionImpl()
1186 Register Reg0 = ChangeReg0 ? Reg2 : MI.getOperand(0).getReg(); in commuteInstructionImpl() local
1189 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead)) in commuteInstructionImpl()

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