Home
last modified time | relevance | path

Searched refs:Reg0 (Results 1 – 25 of 26) sorted by relevance

12

/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsTargetStreamer.h121 void emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc,
125 void emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, SMLoc IDLoc,
127 void emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, SMLoc IDLoc,
129 void emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, SMLoc IDLoc,
131 void emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, MCOperand Op2,
133 void emitRRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
135 void emitRRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, unsigned Reg2,
137 void emitRRI(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm,
139 void emitRRIII(unsigned Opcode, unsigned Reg0, unsigned Reg1, int16_t Imm0,
H A DMipsSEFrameLowering.cpp461 unsigned Reg0 = in emitPrologue() local
467 std::swap(Reg0, Reg1); in emitPrologue()
470 MCCFIInstruction::createOffset(nullptr, Reg0, Offset)); in emitPrologue()
479 unsigned Reg0 = MRI->getDwarfRegNum(Reg, true); in emitPrologue() local
483 std::swap(Reg0, Reg1); in emitPrologue()
486 MCCFIInstruction::createOffset(nullptr, Reg0, Offset)); in emitPrologue()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsTargetStreamer.cpp175 void MipsTargetStreamer::emitR(unsigned Opcode, unsigned Reg0, SMLoc IDLoc, in emitR() argument
179 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitR()
184 void MipsTargetStreamer::emitRX(unsigned Opcode, unsigned Reg0, MCOperand Op1, in emitRX() argument
188 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRX()
194 void MipsTargetStreamer::emitRI(unsigned Opcode, unsigned Reg0, int32_t Imm, in emitRI() argument
196 emitRX(Opcode, Reg0, MCOperand::createImm(Imm), IDLoc, STI); in emitRI()
199 void MipsTargetStreamer::emitRR(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRR() argument
201 emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI); in emitRR()
214 void MipsTargetStreamer::emitRRX(unsigned Opcode, unsigned Reg0, unsigned Reg1, in emitRRX() argument
219 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRRX()
[all …]
H A DMipsMCCodeEmitter.cpp97 unsigned Reg0 = Ctx.getRegisterInfo()->getEncodingValue(RegOp0); in LowerCompactBranch()
102 assert(Reg0 != Reg1 && "Instruction has bad operands ($rs == $rt)!"); in LowerCompactBranch()
103 if (Reg0 < Reg1) in LowerCompactBranch()
106 if (Reg0 >= Reg1) in LowerCompactBranch()
110 if (Reg1 >= Reg0) in LowerCompactBranch()
96 unsigned Reg0 = Ctx.getRegisterInfo()->getEncodingValue(RegOp0); LowerCompactBranch() local
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FixupSetCC.cpp89 Register Reg0 = MI.getOperand(0).getReg(); in runOnMachineFunction() local
90 for (auto &Use : MRI->use_instructions(Reg0)) in runOnMachineFunction()
137 .addReg(Reg0) in runOnMachineFunction()
H A DX86CompressEVEX.cpp193 Register Reg0 = MI.getOperand(0).getReg(); in CompressEVEXImpl() local
199 if (Reg1 == Reg0) in CompressEVEXImpl()
204 !MI.getOperand(2).isReg() || MI.getOperand(2).getReg() != Reg0) in CompressEVEXImpl()
H A DX86ExpandPseudo.cpp467 Register Reg0 = TRI->getSubReg(Reg, X86::sub_mask_0); in expandMI() local
472 .addReg(Reg0, RegState::Define | getDeadRegState(DstIsDead)); in expandMI()
503 Register Reg0 = TRI->getSubReg(Reg, X86::sub_mask_0); in expandMI() local
518 MIBLo.addReg(Reg0, getKillRegState(SrcIsKill)); in expandMI()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonPeephole.cpp233 Register Reg0 = Op0.getReg(); in runOnMachineFunction() local
234 const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0); in runOnMachineFunction()
238 if (Reg0.isVirtual()) { in runOnMachineFunction()
240 if (unsigned PeepholeSrc = PeepholeMap.lookup(Reg0)) { in runOnMachineFunction()
H A DHexagonBitTracker.cpp314 unsigned Reg0 = Reg[0].Reg; in evaluate() local
845 return rr0(eSXT(RegisterCell::self(0, W0).regify(Reg0), 8), Outputs); in evaluate()
847 return rr0(eSXT(RegisterCell::self(0, W0).regify(Reg0), 16), Outputs); in evaluate()
849 return rr0(eZXT(RegisterCell::self(0, W0).regify(Reg0), 8), Outputs); in evaluate()
851 return rr0(eZXT(RegisterCell::self(0, W0).regify(Reg0), 16), Outputs); in evaluate()
/freebsd/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCRegisterInfo.h701 uint16_t Reg0 = 0; variable
709 Reg0 = MCRI->RegUnitRoots[RegUnit][0]; in MCRegUnitRootIterator()
715 return Reg0;
720 return Reg0; in isValid()
726 Reg0 = Reg1;
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp2173 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVLD() local
2195 Ops.push_back(Reg0); in SelectVLD()
2198 Ops.push_back(Reg0); in SelectVLD()
2211 const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain }; in SelectVLD()
2224 Ops.push_back(Reg0); in SelectVLD()
2228 Ops.push_back(Reg0); in SelectVLD()
2308 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); in SelectVST() local
2355 Ops.push_back(Reg0); in SelectVST()
2359 Ops.push_back(Reg0); in SelectVST()
2384 const SDValue OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain }; in SelectVST()
[all …]
H A DThumb2SizeReduction.cpp754 Register Reg0 = MI->getOperand(0).getReg(); in ReduceTo2Addr() local
760 if (!isARMLowRegister(Reg0) || !isARMLowRegister(Reg1) in ReduceTo2Addr()
763 if (Reg0 != Reg2) { in ReduceTo2Addr()
766 if (Reg1 != Reg0) in ReduceTo2Addr()
773 } else if (Reg0 != Reg1) { in ReduceTo2Addr()
778 MI->getOperand(CommOpIdx2).getReg() != Reg0) in ReduceTo2Addr()
785 if (Entry.LowRegs2 && !isARMLowRegister(Reg0)) in ReduceTo2Addr()
H A DARMAsmPrinter.cpp336 Register Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0); in PrintAsmOperand() local
337 O << ARMInstPrinter::getRegisterName(Reg0) << ", "; in PrintAsmOperand()
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp234 Register Reg0 = cast<RegisterSDNode>(V0)->getReg(); in tryInlineAsm() local
256 SDValue T0 = CurDAG->getCopyToReg(Sub0, dl, Reg0, Sub0, in tryInlineAsm()
270 SDValue T0 = CurDAG->getCopyFromReg(Chain, dl, Reg0, MVT::i32, in tryInlineAsm()
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVLegalizerInfo.cpp346 Register Reg0 = Op0.getReg(); in legalizeCustom() local
352 MRI.getType(Reg0).isPointer() && MRI.getType(Reg1).isPointer()) { in legalizeCustom()
357 Op0.setReg(convertPtrToInt(Reg0, ConvT, SpirvTy, Helper, MRI, GR)); in legalizeCustom()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelDAGToDAG.cpp200 unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg(); in selectInlineAsm() local
223 CurDAG->getCopyToReg(Sub0, dl, Reg0, Sub0, RegCopy.getValue(1)); in selectInlineAsm()
237 CurDAG->getCopyFromReg(Chain, dl, Reg0, MVT::i32, Chain.getValue(1)); in selectInlineAsm()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineInstr.cpp2521 Register Reg0 = getOperand(0).getReg(); in getFirst2RegLLTs() local
2523 return std::tuple(Reg0, getRegInfo()->getType(Reg0), Reg1, in getFirst2RegLLTs()
2529 Register Reg0 = getOperand(0).getReg(); in getFirst3RegLLTs() local
2532 return std::tuple(Reg0, getRegInfo()->getType(Reg0), Reg1, in getFirst3RegLLTs()
2539 Register Reg0 = getOperand(0).getReg(); in getFirst4RegLLTs() local
2544 Reg0, getRegInfo()->getType(Reg0), Reg1, getRegInfo()->getType(Reg1), in getFirst4RegLLTs()
2551 Register Reg0 = getOperand(0).getReg(); in getFirst5RegLLTs() local
2557 Reg0, getRegInfo()->getType(Reg0), Reg1, getRegInfo()->getType(Reg1), in getFirst5RegLLTs()
H A DTargetInstrInfo.cpp185 Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register(); in commuteInstructionImpl() local
205 if (HasDef && Reg0 == Reg1 && in commuteInstructionImpl()
208 Reg0 = Reg2; in commuteInstructionImpl()
210 } else if (HasDef && Reg0 == Reg2 && in commuteInstructionImpl()
213 Reg0 = Reg1; in commuteInstructionImpl()
227 CommutedMI->getOperand(0).setReg(Reg0); in commuteInstructionImpl()
H A DRegisterCoalescer.cpp2719 Register Reg0; in valuesIdentical() local
2720 std::tie(Orig0, Reg0) = followCopyChain(Value0); in valuesIdentical()
2721 if (Orig0 == Value1 && Reg0 == Other.Reg) in valuesIdentical()
2731 return Orig0 == Orig1 && Reg0 == Reg1; in valuesIdentical()
2737 return Orig0->def == Orig1->def && Reg0 == Reg1; in valuesIdentical()
H A DRegAllocFast.cpp1339 Register Reg0 = MO0.getReg(); in findAndSortDefOperandIndexes() local
1341 const TargetRegisterClass &RC0 = *MRI->getRegClass(Reg0); in findAndSortDefOperandIndexes()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMInstPrinter.cpp1494 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwo() local
1497 printRegName(O, Reg0); in printVectorListTwo()
1507 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoSpaced() local
1510 printRegName(O, Reg0); in printVectorListTwoSpaced()
1562 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoAllLanes() local
1565 printRegName(O, Reg0); in printVectorListTwoAllLanes()
1609 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0); in printVectorListTwoSpacedAllLanes() local
1612 printRegName(O, Reg0); in printVectorListTwoSpacedAllLanes()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FrameLowering.cpp1246 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg()); in InsertSEH() local
1249 .addImm(Reg0) in InsertSEH()
1259 Register Reg0 = MBBI->getOperand(1).getReg(); in InsertSEH() local
1261 if (Reg0 == AArch64::FP && Reg1 == AArch64::LR) in InsertSEH()
1267 .addImm(RegInfo->getSEHRegNum(Reg0)) in InsertSEH()
1297 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg()); in InsertSEH() local
1300 .addImm(Reg0) in InsertSEH()
1308 Register Reg0 = MBBI->getOperand(0).getReg(); in InsertSEH() local
1310 if (Reg0 == AArch64::FP && Reg1 == AArch64::LR) in InsertSEH()
1316 .addImm(RegInfo->getSEHRegNum(Reg0)) in InsertSEH()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFoldOperands.cpp985 Register Reg0 = UseMI->getOperand(0).getReg(); in foldOperand() local
987 if (TRI->isAGPR(*MRI, Reg0) && TRI->isVGPR(*MRI, Reg1)) in foldOperand()
989 else if (TRI->isVGPR(*MRI, Reg0) && TRI->isAGPR(*MRI, Reg1)) in foldOperand()
991 else if (ST->hasGFX90AInsts() && TRI->isAGPR(*MRI, Reg0) && in foldOperand()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp2229 Register Reg0 = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass); in loadImmediate() local
2231 BuildMI(MBB, MBBI, DL, get(SystemZ::IMPLICIT_DEF), Reg0); in loadImmediate()
2233 .addReg(Reg0).addImm(Value >> 32); in loadImmediate()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp1158 Register Reg0 = MI.getOperand(0).getReg(); in commuteInstructionImpl() local
1168 if (Reg0 == Reg1) { in commuteInstructionImpl()
1188 Register Reg0 = ChangeReg0 ? Reg2 : MI.getOperand(0).getReg(); in commuteInstructionImpl() local
1191 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead)) in commuteInstructionImpl()

12