| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | Register.h | 20 unsigned Reg; variable
23 constexpr Register(unsigned Val = 0) : Reg(Val) {} in Reg() function
24 constexpr Register(MCRegister Val) : Reg(Val) {} in Register()
36 static_assert(std::numeric_limits<decltype(Reg)>::max() >= 0xFFFFFFFF,
44 static constexpr bool isStackSlot(unsigned Reg) { in isStackSlot() argument
45 return MCRegister::isStackSlot(Reg); in isStackSlot()
49 constexpr bool isStack() const { return MCRegister::isStackSlot(Reg); } in isStack()
52 static int stackSlot2Index(Register Reg) { in stackSlot2Index() argument
53 assert(Reg.isStack() && "Not a stack slot"); in stackSlot2Index()
54 return int(Reg - MCRegister::FirstStackSlot); in stackSlot2Index()
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| H A D | MachineRegisterInfo.h | 59 virtual void MRI_NoteNewVirtualRegister(Register Reg) = 0;
129 return MO->Contents.Reg.Next; in getNextOperandForReg()
177 void noteNewVirtualRegister(Register Reg) { in noteNewVirtualRegister() argument
179 TheDelegate->MRI_NoteNewVirtualRegister(Reg); in noteNewVirtualRegister()
249 void disableCalleeSavedRegister(MCRegister Reg);
270 void verifyUseList(Register Reg) const;
300 inline iterator_range<reg_iterator> reg_operands(Register Reg) const { in reg_operands() argument
301 return make_range(reg_begin(Reg), reg_end()); in reg_operands()
316 reg_instructions(Register Reg) const { in reg_instructions() argument
317 return make_range(reg_instr_begin(Reg), reg_instr_end()); in reg_instructions()
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| H A D | LiveIntervals.h | 125 LiveInterval &getInterval(Register Reg) { in getInterval() argument
126 if (hasInterval(Reg)) in getInterval()
127 return *VirtRegIntervals[Reg.id()]; in getInterval()
129 return createAndComputeVirtRegInterval(Reg); in getInterval()
132 const LiveInterval &getInterval(Register Reg) const { in getInterval() argument
133 return const_cast<LiveIntervals *>(this)->getInterval(Reg); in getInterval()
136 bool hasInterval(Register Reg) const { in hasInterval() argument
137 return VirtRegIntervals.inBounds(Reg.id()) && VirtRegIntervals[Reg.id()]; in hasInterval()
141 LiveInterval &createEmptyInterval(Register Reg) { in createEmptyInterval() argument
142 assert(!hasInterval(Reg) && "Interval already exists!"); in createEmptyInterval()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineRegisterInfo.cpp | 59 MachineRegisterInfo::setRegClass(Register Reg, const TargetRegisterClass *RC) { in setRegClass() argument
61 VRegInfo[Reg].first = RC; in setRegClass()
64 void MachineRegisterInfo::setRegBank(Register Reg, in setRegBank() argument
66 VRegInfo[Reg].first = &RegBank; in setRegBank()
70 constrainRegClass(MachineRegisterInfo &MRI, Register Reg, in constrainRegClass() argument
81 MRI.setRegClass(Reg, NewRC); in constrainRegClass()
86 Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs) { in constrainRegClass() argument
87 if (Reg.isPhysical()) in constrainRegClass()
89 return ::constrainRegClass(*this, Reg, getRegClass(Reg), RC, MinNumRegs); in constrainRegClass()
93 MachineRegisterInfo::constrainRegAttrs(Register Reg, in constrainRegAttrs() argument
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| H A D | AggressiveAntiDepBreaker.cpp | 70 unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) { in GetGroup() argument
71 unsigned Node = GroupNodeIndices[Reg]; in GetGroup()
83 for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) { in GetGroupRegs() local
84 if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0)) in GetGroupRegs()
85 Regs.push_back(Reg); in GetGroupRegs()
104 unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg) { in LeaveGroup() argument
110 GroupNodeIndices[Reg] = idx; in LeaveGroup()
114 bool AggressiveAntiDepState::IsLive(unsigned Reg) { in IsLive() argument
117 return((KillIndices[Reg] != ~0u) && (DefIndices[Reg] == ~0u)); in IsLive()
158 unsigned Reg = *AI; in StartBlock() local
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| H A D | LiveVariables.cpp | 81 const Register Reg = Register::index2VirtReg(I); in print() local
83 VirtRegInfo[Reg].print(OS); in print()
114 LiveVariables::VarInfo &LiveVariables::getVarInfo(Register Reg) { in getVarInfo() argument
115 assert(Reg.isVirtual() && "getVarInfo: not a virtual register!"); in getVarInfo()
116 VirtRegInfo.grow(Reg); in getVarInfo()
117 return VirtRegInfo[Reg]; in getVarInfo()
157 void LiveVariables::HandleVirtRegUse(Register Reg, MachineBasicBlock *MBB, in HandleVirtRegUse() argument
159 assert(MRI->getVRegDef(Reg) && "Register use before def!"); in HandleVirtRegUse()
163 VarInfo &VRInfo = getVarInfo(Reg); in HandleVirtRegUse()
194 if (MBB == MRI->getVRegDef(Reg)->getParent()) in HandleVirtRegUse()
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| H A D | CriticalAntiDepBreaker.cpp | 70 unsigned Reg = *AI; in StartBlock() local
71 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in StartBlock()
72 KillIndices[Reg] = BBSize; in StartBlock()
73 DefIndices[Reg] = ~0u; in StartBlock()
84 unsigned Reg = *I; in StartBlock() local
85 if (!IsReturnBlock && !Pristine.test(Reg)) in StartBlock()
88 unsigned Reg = *AI; in StartBlock() local
89 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in StartBlock()
90 KillIndices[Reg] = BBSize; in StartBlock()
91 DefIndices[Reg] = ~0u; in StartBlock()
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| H A D | RegisterScavenging.cpp | 51 void RegScavenger::setRegUsed(Register Reg, LaneBitmask LaneMask) { in setRegUsed() argument
52 LiveUnits.addRegMasked(Reg, LaneMask); in setRegUsed()
65 SI.Reg = 0; in init()
89 I.Reg = 0; in enterBasicBlockEnd()
95 bool RegScavenger::isRegUsed(Register Reg, bool includeReserved) const { in enterBasicBlockEnd()
96 if (isReserved(Reg)) in enterBasicBlockEnd()
98 return !LiveUnits.available(Reg); in addRegUnits() argument
102 for (Register Reg : *RC) {
103 if (!isRegUsed(Reg)) { in removeRegUnits() argument
104 LLVM_DEBUG(dbgs() << "Scavenger found unused reg: " << printReg(Reg, TR in removeRegUnits()
137 MCRegister Reg = MO.getReg().asMCReg(); determineKillsAndDefs() local
186 Register Reg = MO.getReg(); forward() local
248 isRegUsed(Register Reg,bool includeReserved) const isRegUsed() argument
305 for (MCPhysReg Reg : AllocationOrder) { findSurvivorBackwards() local
330 for (MCPhysReg Reg : AllocationOrder) { findSurvivorBackwards() local
376 spill(Register Reg,const TargetRegisterClass & RC,int SPAdj,MachineBasicBlock::iterator Before,MachineBasicBlock::iterator & UseMI) spill() argument
462 MCPhysReg Reg = P.first; scavengeRegisterBackwards() local
567 Register Reg = MO.getReg(); scavengeFrameVirtualRegsInBlock() local
589 Register Reg = MO.getReg(); scavengeFrameVirtualRegsInBlock() local
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| H A D | FixupStatepointCallerSaved.cpp | 92 static unsigned getRegisterSize(const TargetRegisterInfo &TRI, Register Reg) { in getRegisterSize() argument
93 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg); in getRegisterSize()
110 static Register performCopyPropagation(Register Reg, in performCopyPropagation() argument
115 int Idx = RI->findRegisterUseOperandIdx(Reg, &TRI, false); in performCopyPropagation()
118 return Reg; in performCopyPropagation()
122 return Reg; in performCopyPropagation()
128 if (It->readsRegister(Reg, &TRI) && !Use) in performCopyPropagation()
130 if (It->modifiesRegister(Reg, &TRI)) { in performCopyPropagation()
137 return Reg; in performCopyPropagation()
140 if (!DestSrc || DestSrc->Destination->getReg() != Reg) in performCopyPropagation()
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| H A D | MachineInstrBundle.cpp | 159 Register Reg = MO.getReg(); in finalizeBundle() local
160 if (!Reg) in finalizeBundle()
163 if (LocalDefSet.count(Reg)) { in finalizeBundle()
167 KilledDefSet.insert(Reg); in finalizeBundle()
169 if (ExternUseSet.insert(Reg).second) { in finalizeBundle()
170 ExternUses.push_back(Reg); in finalizeBundle()
172 UndefUseSet.insert(Reg); in finalizeBundle()
176 KilledUseSet.insert(Reg); in finalizeBundle()
181 Register Reg = MO->getReg(); in finalizeBundle() local
182 if (!Reg) in finalizeBundle()
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| H A D | LivePhysRegs.cpp | 87 Register Reg = O->getReg(); in stepForward() local
88 if (!Reg.isPhysical()) in stepForward()
93 Clobbers.push_back(std::make_pair(Reg, &*O)); in stepForward()
97 removeReg(Reg); in stepForward()
105 for (auto Reg : Clobbers) { in stepForward() local
108 if (Reg.second->isReg() && Reg.second->isDead()) in stepForward()
110 if (Reg.second->isRegMask() && in stepForward()
111 MachineOperand::clobbersPhysReg(Reg.second->getRegMask(), Reg.first)) in stepForward()
113 addReg(Reg.first); in stepForward()
142 MCPhysReg Reg) const { in available()
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| H A D | MachineLateInstrsCleanup.cpp | 46 bool hasIdentical(Register Reg, MachineInstr *ArgMI) { in hasIdentical()
47 MachineInstr *MI = lookup(Reg); in hasIdentical()
60 void clearKillsForDef(Register Reg, MachineBasicBlock *MBB,
119 clearKillsForDef(Register Reg, MachineBasicBlock *MBB, in clearKillsForDef() argument
125 if (MachineInstr *KillMI = RegKills[MBB->getNumber()].lookup(Reg)) { in clearKillsForDef()
126 KillMI->clearRegisterKills(Reg, TRI); in clearKillsForDef()
131 if (MachineInstr *DefMI = RegDefs[MBB->getNumber()].lookup(Reg)) in clearKillsForDef()
136 if (!MBB->isLiveIn(Reg)) in clearKillsForDef()
137 MBB->addLiveIn(Reg); in clearKillsForDef()
141 clearKillsForDef(Reg, Pred, Pred->end(), VisitedPreds); in clearKillsForDef()
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| H A D | CalcSpillWeights.cpp | 40 Register Reg = Register::index2VirtReg(I); in calculateSpillWeightsAndHints() local
41 if (MRI.reg_nodbg_empty(Reg)) in calculateSpillWeightsAndHints()
43 calculateSpillWeightAndHint(LIS.getInterval(Reg)); in calculateSpillWeightsAndHints()
48 Register VirtRegAuxInfo::copyHint(const MachineInstr *MI, unsigned Reg, in copyHint() argument
53 if (MI->getOperand(0).getReg() == Reg) { in copyHint()
69 const TargetRegisterClass *RC = MRI.getRegClass(Reg); in copyHint()
86 Register Reg = LI.reg(); in isRematerializable() local
87 Register Original = VRM.getOriginal(Reg); in isRematerializable()
104 if (MI->getOperand(0).getReg() != Reg) in isRematerializable()
108 Reg = MI->getOperand(1).getReg(); in isRematerializable()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64TargetStreamer.h | 51 virtual void emitARM64WinCFISaveReg(unsigned Reg, int Offset) {} in emitARM64WinCFISaveReg() argument
52 virtual void emitARM64WinCFISaveRegX(unsigned Reg, int Offset) {} in emitARM64WinCFISaveRegX() argument
53 virtual void emitARM64WinCFISaveRegP(unsigned Reg, int Offset) {} in emitARM64WinCFISaveRegP() argument
54 virtual void emitARM64WinCFISaveRegPX(unsigned Reg, int Offset) {} in emitARM64WinCFISaveRegPX() argument
55 virtual void emitARM64WinCFISaveLRPair(unsigned Reg, int Offset) {} in emitARM64WinCFISaveLRPair() argument
56 virtual void emitARM64WinCFISaveFReg(unsigned Reg, int Offset) {} in emitARM64WinCFISaveFReg() argument
57 virtual void emitARM64WinCFISaveFRegX(unsigned Reg, int Offset) {} in emitARM64WinCFISaveFRegX() argument
58 virtual void emitARM64WinCFISaveFRegP(unsigned Reg, int Offset) {} in emitARM64WinCFISaveFRegP() argument
59 virtual void emitARM64WinCFISaveFRegPX(unsigned Reg, int Offset) {} in emitARM64WinCFISaveFRegPX() argument
73 virtual void emitARM64WinCFISaveAnyRegI(unsigned Reg, int Offset) {} in emitARM64WinCFISaveAnyRegI() argument
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| H A D | AArch64WinCOFFStreamer.cpp | 70 int Reg, int Offset) { in emitARM64WinUnwindCode() argument
75 auto Inst = WinEH::Instruction(UnwindCode, /*Label=*/nullptr, Reg, Offset); in emitARM64WinUnwindCode()
103 void AArch64TargetWinCOFFStreamer::emitARM64WinCFISaveReg(unsigned Reg, in emitARM64WinCFISaveReg() argument
107 emitARM64WinUnwindCode(Win64EH::UOP_SaveReg, Reg, Offset); in emitARM64WinCFISaveReg()
110 void AArch64TargetWinCOFFStreamer::emitARM64WinCFISaveRegX(unsigned Reg, in emitARM64WinCFISaveRegX() argument
112 emitARM64WinUnwindCode(Win64EH::UOP_SaveRegX, Reg, Offset); in emitARM64WinCFISaveRegX()
115 void AArch64TargetWinCOFFStreamer::emitARM64WinCFISaveRegP(unsigned Reg, in emitARM64WinCFISaveRegP() argument
117 emitARM64WinUnwindCode(Win64EH::UOP_SaveRegP, Reg, Offset); in emitARM64WinCFISaveRegP()
120 void AArch64TargetWinCOFFStreamer::emitARM64WinCFISaveRegPX(unsigned Reg, in emitARM64WinCFISaveRegPX() argument
122 emitARM64WinUnwindCode(Win64EH::UOP_SaveRegPX, Reg, Offset); in emitARM64WinCFISaveRegPX()
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| H A D | AArch64ELFStreamer.cpp | 68 void emitARM64WinCFISaveReg(unsigned Reg, int Offset) override { in emitARM64WinCFISaveReg() argument
69 OS << "\t.seh_save_reg\tx" << Reg << ", " << Offset << "\n"; in emitARM64WinCFISaveReg()
71 void emitARM64WinCFISaveRegX(unsigned Reg, int Offset) override { in emitARM64WinCFISaveRegX() argument
72 OS << "\t.seh_save_reg_x\tx" << Reg << ", " << Offset << "\n"; in emitARM64WinCFISaveRegX()
74 void emitARM64WinCFISaveRegP(unsigned Reg, int Offset) override { in emitARM64WinCFISaveRegP() argument
75 OS << "\t.seh_save_regp\tx" << Reg << ", " << Offset << "\n"; in emitARM64WinCFISaveRegP()
77 void emitARM64WinCFISaveRegPX(unsigned Reg, int Offset) override { in emitARM64WinCFISaveRegPX() argument
78 OS << "\t.seh_save_regp_x\tx" << Reg << ", " << Offset << "\n"; in emitARM64WinCFISaveRegPX()
80 void emitARM64WinCFISaveLRPair(unsigned Reg, int Offset) override { in emitARM64WinCFISaveLRPair() argument
81 OS << "\t.seh_save_lrpair\tx" << Reg << ", " << Offset << "\n"; in emitARM64WinCFISaveLRPair()
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| H A D | AArch64InstPrinter.cpp | 62 void AArch64InstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) const { in printRegName()
63 markup(OS, Markup::Register) << getRegisterName(Reg); in printRegName()
66 void AArch64InstPrinter::printRegName(raw_ostream &OS, MCRegister Reg, in printRegName() argument
68 markup(OS, Markup::Register) << getRegisterName(Reg, AltIdx); in printRegName()
71 StringRef AArch64InstPrinter::getRegName(MCRegister Reg) const { in getRegName()
72 return getRegisterName(Reg); in getRegName()
825 unsigned Reg = MI->getOperand(OpNum++).getReg(); in printInst()
826 if (Reg != AArch64::XZR) { in printInst()
828 printRegName(O, Reg); in getRegName()
843 StringRef AArch64AppleInstPrinter::getRegName(MCRegister Reg) cons in printRangePrefetchAlias()
810 unsigned Reg = MI->getOperand(OpNum++).getReg(); printInst() local
1131 unsigned Reg = Op.getReg(); printOperand() local
1174 unsigned Reg = Op.getReg(); printPostIncOperand() local
1188 unsigned Reg = Op.getReg(); printVRegOperand() local
1337 unsigned Reg = MI->getOperand(OpNum).getReg(); printPredicateAsCounter() local
1494 getNextVectorRegister(unsigned Reg,unsigned Stride=1) getNextVectorRegister() argument
1598 unsigned Reg = MI->getOperand(OpNum).getReg(); printGPRSeqPairsClassOperand() local
1624 unsigned Reg = RegMask & (1 << I); printMatrixTileList() local
1639 unsigned Reg = MI->getOperand(OpNum).getReg(); printVectorList() local
1849 isValidSysReg(const AArch64SysReg::SysReg * Reg,bool Read,const MCSubtargetInfo & STI) isValidSysReg() argument
1863 const AArch64SysReg::SysReg *Reg = AArch64SysReg::lookupSysRegByEncoding(Val); lookupSysReg() local
1890 const AArch64SysReg::SysReg *Reg = lookupSysReg(Val, true /*Read*/, STI); printMRSSystemRegister() local
1917 const AArch64SysReg::SysReg *Reg = lookupSysReg(Val, false /*Read*/, STI); printMSRSystemRegister() local
1996 unsigned Reg = MI->getOperand(OpNum).getReg(); printSVERegOp() local
2078 unsigned Reg = MI->getOperand(OpNum).getReg(); printZPRasFPR() local
2096 unsigned Reg = MI->getOperand(OpNum).getReg(); printGPR64as32() local
2103 unsigned Reg = MI->getOperand(OpNum).getReg(); printGPR64x8() local
2110 unsigned Reg = MI->getOperand(OpNum).getReg(); printSyspXzrPair() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonVectorPrint.cpp | 73 static bool isVecReg(unsigned Reg) { in isVecReg() argument
74 return (Reg >= Hexagon::V0 && Reg <= Hexagon::V31) || in isVecReg()
75 (Reg >= Hexagon::W0 && Reg <= Hexagon::W15) || in isVecReg()
76 (Reg >= Hexagon::WR0 && Reg <= Hexagon::WR15) || in isVecReg()
77 (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3); in isVecReg()
96 static void addAsmInstr(MachineBasicBlock *MBB, unsigned Reg, in addAsmInstr() argument
100 std::string VDescStr = ".long 0x1dffe0" + getStringReg(Reg); in addAsmInstr()
108 static bool getInstrVecReg(const MachineInstr &MI, unsigned &Reg) { in getInstrVecReg() argument
112 Reg = MI.getOperand(0).getReg(); in getInstrVecReg()
113 if (isVecReg(Reg)) in getInstrVecReg()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCRegister.h | 35 unsigned Reg; variable
38 constexpr MCRegister(unsigned Val = 0) : Reg(Val) {} in Reg() function
50 static_assert(std::numeric_limits<decltype(Reg)>::max() >= 0xFFFFFFFF,
61 static constexpr bool isStackSlot(unsigned Reg) { in isStackSlot() argument
62 return FirstStackSlot <= Reg && Reg < VirtualRegFlag; in isStackSlot()
67 static constexpr bool isPhysicalRegister(unsigned Reg) { in isPhysicalRegister() argument
68 return FirstPhysicalReg <= Reg && Reg < FirstStackSlot; in isPhysicalRegister()
71 constexpr operator unsigned() const { return Reg; }
79 constexpr unsigned id() const { return Reg; } in id()
81 constexpr bool isValid() const { return Reg != NoRegister; } in isValid()
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| H A D | MCRegisterInfo.h | 73 bool contains(MCRegister Reg) const { in contains() argument
74 unsigned RegNo = unsigned(Reg); in contains()
238 iterator_range<MCSubRegIterator> subregs(MCRegister Reg) const;
242 iterator_range<MCSubRegIterator> subregs_inclusive(MCRegister Reg) const;
246 iterator_range<MCSuperRegIterator> superregs(MCRegister Reg) const;
250 iterator_range<MCSuperRegIterator> superregs_inclusive(MCRegister Reg) const;
256 sub_and_superregs_inclusive(MCRegister Reg) const;
259 iterator_range<MCRegUnitIterator> regunits(MCRegister Reg) const;
376 MCRegister getSubReg(MCRegister Reg, unsigned Idx) const;
380 MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUResourceUsageAnalysis.cpp | 72 const SIInstrInfo &TII, unsigned Reg) { in hasAnyNonFlatUseOfReg() argument
73 for (const MachineOperand &UseOp : MRI.reg_operands(Reg)) { in hasAnyNonFlatUseOfReg()
218 for (MCPhysReg Reg : reverse(AMDGPU::VGPR_32RegClass.getRegisters())) { in analyzeResourceUsage() local
219 if (MRI.isPhysRegUsed(Reg)) { in analyzeResourceUsage()
220 HighestVGPRReg = Reg; in analyzeResourceUsage()
227 for (MCPhysReg Reg : reverse(AMDGPU::AGPR_32RegClass.getRegisters())) { in analyzeResourceUsage() local
228 if (MRI.isPhysRegUsed(Reg)) { in analyzeResourceUsage()
229 HighestAGPRReg = Reg; in analyzeResourceUsage()
239 for (MCPhysReg Reg : reverse(AMDGPU::SGPR_32RegClass.getRegisters())) { in analyzeResourceUsage() local
240 if (MRI.isPhysRegUsed(Reg)) { in analyzeResourceUsage()
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| H A D | SIProgramInfo.cpp | 80 uint64_t Reg = S_00B848_PRIORITY(ProgInfo.Priority) | in getComputePGMRSrc1Reg() local
88 Reg |= S_00B848_DX10_CLAMP(ProgInfo.DX10Clamp); in getComputePGMRSrc1Reg()
91 Reg |= S_00B848_IEEE_MODE(ProgInfo.IEEEMode); in getComputePGMRSrc1Reg()
94 Reg |= S_00B848_RR_WG_MODE(ProgInfo.RrWgMode); in getComputePGMRSrc1Reg()
96 return Reg; in getComputePGMRSrc1Reg()
101 uint64_t Reg = S_00B848_PRIORITY(ProgInfo.Priority) | in getPGMRSrc1Reg() local
107 Reg |= S_00B848_DX10_CLAMP(ProgInfo.DX10Clamp); in getPGMRSrc1Reg()
110 Reg |= S_00B848_IEEE_MODE(ProgInfo.IEEEMode); in getPGMRSrc1Reg()
113 Reg |= S_00B848_RR_WG_MODE(ProgInfo.RrWgMode); in getPGMRSrc1Reg()
117 Reg |= S_00B028_MEM_ORDERED(ProgInfo.MemOrdered); in getPGMRSrc1Reg()
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| H A D | SIOptimizeVGPRLiveRange.cpp | 120 void findNonPHIUsesInBlock(Register Reg, MachineBasicBlock *MBB,
123 void updateLiveRangeInThenRegion(Register Reg, MachineBasicBlock *If,
127 Register Reg, Register NewReg, MachineBasicBlock *Flow,
132 optimizeLiveRange(Register Reg, MachineBasicBlock *If,
137 Register Reg, MachineBasicBlock *LoopHeader,
212 Register Reg, MachineBasicBlock *MBB, in findNonPHIUsesInBlock() argument
214 for (auto &UseMI : MRI->use_nodbg_instructions(Reg)) { in findNonPHIUsesInBlock()
279 Register Reg = MO.getReg(); in collectCandidateRegisters() local
280 if (Reg.isPhysical() || !TRI->isVectorRegister(*MRI, Reg)) in collectCandidateRegisters()
283 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg); in collectCandidateRegisters()
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| /freebsd/sys/contrib/dev/acpica/components/hardware/ |
| H A D | hwregs.c | 168 ACPI_GENERIC_ADDRESS *Reg,
203 ACPI_GENERIC_ADDRESS *Reg, in AcpiHwGetAccessBitWidth() argument
223 if (!Reg->BitOffset && Reg->BitWidth && in AcpiHwGetAccessBitWidth()
224 ACPI_IS_POWER_OF_TWO (Reg->BitWidth) && in AcpiHwGetAccessBitWidth()
225 ACPI_IS_ALIGNED (Reg->BitWidth, 8)) in AcpiHwGetAccessBitWidth()
227 AccessBitWidth = Reg->BitWidth; in AcpiHwGetAccessBitWidth()
229 else if (Reg->AccessWidth) in AcpiHwGetAccessBitWidth()
231 AccessBitWidth = ACPI_ACCESS_BIT_WIDTH (Reg->AccessWidth); in AcpiHwGetAccessBitWidth()
236 Reg->BitOffset + Reg->BitWidth); in AcpiHwGetAccessBitWidth()
252 if (Reg->SpaceId == ACPI_ADR_SPACE_SYSTEM_IO) in AcpiHwGetAccessBitWidth()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | MLxExpansionPass.cpp | 65 bool hasRAWHazard(unsigned Reg, MachineInstr *MI) const;
89 Register Reg = MI->getOperand(1).getReg(); in getAccDefMI() local
90 if (Reg.isPhysical()) in getAccDefMI()
94 MachineInstr *DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
99 Reg = DefMI->getOperand(1).getReg(); in getAccDefMI()
100 if (Reg.isVirtual()) { in getAccDefMI()
101 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
105 Reg = DefMI->getOperand(2).getReg(); in getAccDefMI()
106 if (Reg.isVirtual()) { in getAccDefMI()
107 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
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