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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineRegisterInfo.cpp58 MachineRegisterInfo::setRegClass(Register Reg, const TargetRegisterClass *RC) { in setRegClass() argument
60 VRegInfo[Reg].first = RC; in setRegClass()
63 void MachineRegisterInfo::setRegBank(Register Reg, in setRegBank() argument
65 VRegInfo[Reg].first = &RegBank; in setRegBank()
69 constrainRegClass(MachineRegisterInfo &MRI, Register Reg, in constrainRegClass() argument
80 MRI.setRegClass(Reg, NewRC); in constrainRegClass()
85 Register Reg, const TargetRegisterClass *RC, unsigned MinNumRegs) { in constrainRegClass() argument
86 if (Reg.isPhysical()) in constrainRegClass()
88 return ::constrainRegClass(*this, Reg, getRegClass(Reg), RC, MinNumRegs); in constrainRegClass()
92 MachineRegisterInfo::constrainRegAttrs(Register Reg, in constrainRegAttrs() argument
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H A DAggressiveAntiDepBreaker.cpp70 unsigned AggressiveAntiDepState::GetGroup(MCRegister Reg) { in GetGroup() argument
71 unsigned Node = GroupNodeIndices[Reg]; in GetGroup()
82 for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) { in GetGroupRegs() local
83 if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0)) in GetGroupRegs()
84 Regs.push_back(Reg); in GetGroupRegs()
103 unsigned AggressiveAntiDepState::LeaveGroup(MCRegister Reg) { in LeaveGroup() argument
109 GroupNodeIndices[Reg] = idx; in LeaveGroup()
113 bool AggressiveAntiDepState::IsLive(MCRegister Reg) { in IsLive() argument
116 return((KillIndices[Reg] != ~0u) && (DefIndices[Reg] == ~0u)); in IsLive()
157 unsigned Reg = *AI; in StartBlock() local
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H A DLiveVariables.cpp80 const Register Reg = Register::index2VirtReg(I); in print() local
82 VirtRegInfo[Reg].print(OS); in print()
113 LiveVariables::VarInfo &LiveVariables::getVarInfo(Register Reg) { in getVarInfo() argument
114 assert(Reg.isVirtual() && "getVarInfo: not a virtual register!"); in getVarInfo()
115 VirtRegInfo.grow(Reg); in getVarInfo()
116 return VirtRegInfo[Reg]; in getVarInfo()
156 void LiveVariables::HandleVirtRegUse(Register Reg, MachineBasicBlock *MBB, in HandleVirtRegUse() argument
158 assert(MRI->getVRegDef(Reg) && "Register use before def!"); in HandleVirtRegUse()
162 VarInfo &VRInfo = getVarInfo(Reg); in HandleVirtRegUse()
193 if (MBB == MRI->getVRegDef(Reg)->getParent()) in HandleVirtRegUse()
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H A DCriticalAntiDepBreaker.cpp70 MCRegister Reg = *AI; in StartBlock() local
71 Classes[Reg.id()] = reinterpret_cast<TargetRegisterClass *>(-1); in StartBlock()
72 KillIndices[Reg.id()] = BBSize; in StartBlock()
73 DefIndices[Reg] = ~0u; in StartBlock()
84 unsigned Reg = *I; in StartBlock() local
85 if (!IsReturnBlock && !Pristine.test(Reg)) in StartBlock()
88 MCRegister Reg = *AI; in StartBlock() local
89 Classes[Reg.id()] = reinterpret_cast<TargetRegisterClass *>(-1); in StartBlock()
90 KillIndices[Reg.id()] = BBSize; in StartBlock()
91 DefIndices[Reg.id()] = ~0u; in StartBlock()
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H A DFixupStatepointCallerSaved.cpp97 static unsigned getRegisterSize(const TargetRegisterInfo &TRI, Register Reg) { in getRegisterSize() argument
98 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg); in getRegisterSize()
115 static Register performCopyPropagation(Register Reg, in performCopyPropagation() argument
120 int Idx = RI->findRegisterUseOperandIdx(Reg, &TRI, false); in performCopyPropagation()
123 return Reg; in performCopyPropagation()
127 return Reg; in performCopyPropagation()
133 if (It->readsRegister(Reg, &TRI) && !Use) in performCopyPropagation()
135 if (It->modifiesRegister(Reg, &TRI)) { in performCopyPropagation()
142 return Reg; in performCopyPropagation()
145 if (!DestSrc || DestSrc->Destination->getReg() != Reg) in performCopyPropagation()
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H A DReachingDefAnalysis.cpp39 static bool isValidRegUseOf(const MachineOperand &MO, Register Reg, in isValidRegUseOf() argument
43 return TRI->regsOverlap(MO.getReg(), Reg); in isValidRegUseOf()
50 static bool isValidRegDefOf(const MachineOperand &MO, Register Reg, in isValidRegDefOf() argument
54 return TRI->regsOverlap(MO.getReg(), Reg); in isValidRegDefOf()
243 Register Reg; in printAllReachingDefs() local
248 Reg = Register::index2StackSlot(FrameIndex); in printAllReachingDefs()
252 Reg = MO.getReg(); in printAllReachingDefs()
253 if (!Reg.isValid()) in printAllReachingDefs()
258 getGlobalReachingDefs(&MI, Reg, Defs); in printAllReachingDefs()
335 int ReachingDefAnalysis::getReachingDef(MachineInstr *MI, Register Reg) const { in getReachingDef()
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H A DLivePhysRegs.cpp87 Register Reg = O->getReg(); in stepForward() local
88 if (!Reg.isPhysical()) in stepForward()
93 Clobbers.push_back(std::make_pair(Reg.id(), &*O)); in stepForward()
97 removeReg(Reg); in stepForward()
105 for (auto Reg : Clobbers) { in stepForward() local
108 if (Reg.second->isReg() && Reg.second->isDead()) in stepForward()
110 if (Reg.second->isRegMask() && in stepForward()
111 MachineOperand::clobbersPhysReg(Reg.second->getRegMask(), Reg.first)) in stepForward()
113 addReg(Reg.first); in stepForward()
142 MCRegister Reg) const { in available()
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H A DRegisterScavenging.cpp50 void RegScavenger::setRegUsed(Register Reg, LaneBitmask LaneMask) { in setRegUsed() argument
51 LiveUnits.addRegMasked(Reg, LaneMask); in setRegUsed()
64 SI.Reg = 0; in init()
88 I.Reg = 0; in backward()
94 bool RegScavenger::isRegUsed(Register Reg, bool includeReserved) const { in isRegUsed() argument
95 if (isReserved(Reg)) in isRegUsed()
97 return !LiveUnits.available(Reg); in isRegUsed()
101 for (Register Reg : *RC) { in FindUnusedReg()
102 if (!isRegUsed(Reg)) { in FindUnusedReg()
103 LLVM_DEBUG(dbgs() << "Scavenger found unused reg: " << printReg(Reg, TRI) in FindUnusedReg()
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H A DMachineInstrBundle.cpp150 Register Reg = MO.getReg(); in finalizeBundle() local
151 if (!Reg) in finalizeBundle()
154 if (LocalDefs.contains(Reg)) { in finalizeBundle()
158 KilledDefSet.insert(Reg); in finalizeBundle()
161 if (ExternUses.insert(Reg)) { in finalizeBundle()
163 UndefUseSet.insert(Reg); in finalizeBundle()
167 KilledUseSet.insert(Reg); in finalizeBundle()
173 Register Reg = MO.getReg(); in finalizeBundle() local
174 if (!Reg) in finalizeBundle()
177 if (LocalDefs.insert(Reg)) { in finalizeBundle()
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H A DCalcSpillWeights.cpp39 Register Reg = Register::index2VirtReg(I); in calculateSpillWeightsAndHints() local
40 if (MRI.reg_nodbg_empty(Reg)) in calculateSpillWeightsAndHints()
42 calculateSpillWeightAndHint(LIS.getInterval(Reg)); in calculateSpillWeightsAndHints()
47 Register VirtRegAuxInfo::copyHint(const MachineInstr *MI, Register Reg, in copyHint() argument
52 if (MI->getOperand(0).getReg() == Reg) { in copyHint()
68 const TargetRegisterClass *RC = MRI.getRegClass(Reg); in copyHint()
85 Register Reg = LI.reg(); in isRematerializable() local
86 Register Original = VRM.getOriginal(Reg); in isRematerializable()
103 if (MI->getOperand(0).getReg() != Reg) in isRematerializable()
107 Reg = MI->getOperand(1).getReg(); in isRematerializable()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DRegister.h20 unsigned Reg; variable
23 constexpr Register(unsigned Val = 0) : Reg(Val) {} in Reg() function
24 constexpr Register(MCRegister Val) : Reg(Val.id()) {} in Register()
36 static_assert(std::numeric_limits<decltype(Reg)>::max() >= 0xFFFFFFFF,
44 return Register::FirstStackSlot <= Reg && Reg < Register::VirtualRegFlag; in isStack()
55 static constexpr bool isPhysicalRegister(unsigned Reg) { in isPhysicalRegister() argument
56 return MCRegister::isPhysicalRegister(Reg); in isPhysicalRegister()
61 static constexpr bool isVirtualRegister(unsigned Reg) { in isVirtualRegister() argument
62 return Reg & Register::VirtualRegFlag; in isVirtualRegister()
74 constexpr bool isVirtual() const { return isVirtualRegister(Reg); } in isVirtual()
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H A DMachineRegisterInfo.h61 virtual void MRI_NoteNewVirtualRegister(Register Reg) = 0;
131 return MO->Contents.Reg.Next; in getNextOperandForReg()
179 void noteNewVirtualRegister(Register Reg) { in noteNewVirtualRegister() argument
181 TheDelegate->MRI_NoteNewVirtualRegister(Reg); in noteNewVirtualRegister()
244 LLVM_ABI void disableCalleeSavedRegister(MCRegister Reg);
266 LLVM_ABI void verifyUseList(Register Reg) const;
291 inline iterator_range<reg_iterator> reg_operands(Register Reg) const { in reg_operands() argument
292 return make_range(reg_begin(Reg), reg_end()); in reg_operands()
307 reg_instructions(Register Reg) const { in reg_instructions() argument
308 return make_range(reg_instr_begin(Reg), reg_instr_end()); in reg_instructions()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64TargetStreamer.h65 virtual void emitARM64WinCFISaveReg(unsigned Reg, int Offset) {} in emitARM64WinCFISaveReg() argument
66 virtual void emitARM64WinCFISaveRegX(unsigned Reg, int Offset) {} in emitARM64WinCFISaveRegX() argument
67 virtual void emitARM64WinCFISaveRegP(unsigned Reg, int Offset) {} in emitARM64WinCFISaveRegP() argument
68 virtual void emitARM64WinCFISaveRegPX(unsigned Reg, int Offset) {} in emitARM64WinCFISaveRegPX() argument
69 virtual void emitARM64WinCFISaveLRPair(unsigned Reg, int Offset) {} in emitARM64WinCFISaveLRPair() argument
70 virtual void emitARM64WinCFISaveFReg(unsigned Reg, int Offset) {} in emitARM64WinCFISaveFReg() argument
71 virtual void emitARM64WinCFISaveFRegX(unsigned Reg, int Offset) {} in emitARM64WinCFISaveFRegX() argument
72 virtual void emitARM64WinCFISaveFRegP(unsigned Reg, int Offset) {} in emitARM64WinCFISaveFRegP() argument
73 virtual void emitARM64WinCFISaveFRegPX(unsigned Reg, int Offset) {} in emitARM64WinCFISaveFRegPX() argument
87 virtual void emitARM64WinCFISaveAnyRegI(unsigned Reg, int Offset) {} in emitARM64WinCFISaveAnyRegI() argument
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H A DAArch64WinCOFFStreamer.cpp70 int Reg, int Offset) { in emitARM64WinUnwindCode() argument
75 auto Inst = WinEH::Instruction(UnwindCode, /*Label=*/nullptr, Reg, Offset); in emitARM64WinUnwindCode()
103 void AArch64TargetWinCOFFStreamer::emitARM64WinCFISaveReg(unsigned Reg, in emitARM64WinCFISaveReg() argument
107 emitARM64WinUnwindCode(Win64EH::UOP_SaveReg, Reg, Offset); in emitARM64WinCFISaveReg()
110 void AArch64TargetWinCOFFStreamer::emitARM64WinCFISaveRegX(unsigned Reg, in emitARM64WinCFISaveRegX() argument
112 emitARM64WinUnwindCode(Win64EH::UOP_SaveRegX, Reg, Offset); in emitARM64WinCFISaveRegX()
115 void AArch64TargetWinCOFFStreamer::emitARM64WinCFISaveRegP(unsigned Reg, in emitARM64WinCFISaveRegP() argument
117 emitARM64WinUnwindCode(Win64EH::UOP_SaveRegP, Reg, Offset); in emitARM64WinCFISaveRegP()
120 void AArch64TargetWinCOFFStreamer::emitARM64WinCFISaveRegPX(unsigned Reg, in emitARM64WinCFISaveRegPX() argument
122 emitARM64WinUnwindCode(Win64EH::UOP_SaveRegPX, Reg, Offset); in emitARM64WinCFISaveRegPX()
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H A DAArch64ELFStreamer.cpp78 void emitARM64WinCFISaveReg(unsigned Reg, int Offset) override { in emitARM64WinCFISaveReg() argument
79 OS << "\t.seh_save_reg\tx" << Reg << ", " << Offset << "\n"; in emitARM64WinCFISaveReg()
81 void emitARM64WinCFISaveRegX(unsigned Reg, int Offset) override { in emitARM64WinCFISaveRegX() argument
82 OS << "\t.seh_save_reg_x\tx" << Reg << ", " << Offset << "\n"; in emitARM64WinCFISaveRegX()
84 void emitARM64WinCFISaveRegP(unsigned Reg, int Offset) override { in emitARM64WinCFISaveRegP() argument
85 OS << "\t.seh_save_regp\tx" << Reg << ", " << Offset << "\n"; in emitARM64WinCFISaveRegP()
87 void emitARM64WinCFISaveRegPX(unsigned Reg, int Offset) override { in emitARM64WinCFISaveRegPX() argument
88 OS << "\t.seh_save_regp_x\tx" << Reg << ", " << Offset << "\n"; in emitARM64WinCFISaveRegPX()
90 void emitARM64WinCFISaveLRPair(unsigned Reg, int Offset) override { in emitARM64WinCFISaveLRPair() argument
91 OS << "\t.seh_save_lrpair\tx" << Reg << ", " << Offset << "\n"; in emitARM64WinCFISaveLRPair()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonVectorPrint.cpp65 static bool isVecReg(unsigned Reg) { in isVecReg() argument
66 return (Reg >= Hexagon::V0 && Reg <= Hexagon::V31) || in isVecReg()
67 (Reg >= Hexagon::W0 && Reg <= Hexagon::W15) || in isVecReg()
68 (Reg >= Hexagon::WR0 && Reg <= Hexagon::WR15) || in isVecReg()
69 (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3); in isVecReg()
88 static void addAsmInstr(MachineBasicBlock *MBB, unsigned Reg, in addAsmInstr() argument
92 std::string VDescStr = ".long 0x1dffe0" + getStringReg(Reg); in addAsmInstr()
100 static bool getInstrVecReg(const MachineInstr &MI, unsigned &Reg) { in getInstrVecReg() argument
104 Reg = MI.getOperand(0).getReg(); in getInstrVecReg()
105 if (isVecReg(Reg)) in getInstrVecReg()
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H A DHexagonGenPredicate.cpp47 : Reg(R), TRI(I) {} in PrintRegister()
50 RegSubRegPair Reg; member
57 return OS << printReg(PR.Reg.Reg, &PR.TRI, PR.Reg.SubReg); in operator <<()
92 void processPredicateGPR(const RegSubRegPair &Reg);
97 RegSubRegPair getPredRegFor(const RegSubRegPair &Reg);
191 if (RD.Reg.isVirtual()) in collectPredicateGPR()
200 void HexagonGenPredicate::processPredicateGPR(const RegSubRegPair &Reg) { in processPredicateGPR() argument
201 LLVM_DEBUG(dbgs() << __func__ << ": " << printReg(Reg.Reg, TRI, Reg.SubReg) in processPredicateGPR()
205 use_iterator I = MRI->use_begin(Reg.Reg), E = MRI->use_end(); in processPredicateGPR()
207 LLVM_DEBUG(dbgs() << "Dead reg: " << printReg(Reg.Reg, TRI, Reg.SubReg) in processPredicateGPR()
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/freebsd/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCRegister.h35 unsigned Reg; variable
38 constexpr MCRegister(unsigned Val = 0) : Reg(Val) {} in Reg() function
50 static_assert(std::numeric_limits<decltype(Reg)>::max() >= 0xFFFFFFFF,
58 static constexpr bool isPhysicalRegister(unsigned Reg) { in isPhysicalRegister() argument
59 return FirstPhysicalReg <= Reg && Reg <= LastPhysicalReg; in isPhysicalRegister()
64 constexpr bool isPhysical() const { return isPhysicalRegister(Reg); } in isPhysical()
66 constexpr operator unsigned() const { return Reg; }
74 constexpr unsigned id() const { return Reg; } in id()
76 constexpr bool isValid() const { return Reg != NoRegister; } in isValid()
80 return Reg == Other.Reg;
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H A DMCRegisterInfo.h74 bool contains(MCRegister Reg) const { in contains() argument
75 unsigned RegNo = Reg.id(); in contains()
242 iterator_range<MCSubRegIterator> subregs(MCRegister Reg) const;
246 iterator_range<MCSubRegIterator> subregs_inclusive(MCRegister Reg) const;
250 iterator_range<MCSuperRegIterator> superregs(MCRegister Reg) const;
254 iterator_range<MCSuperRegIterator> superregs_inclusive(MCRegister Reg) const;
260 sub_and_superregs_inclusive(MCRegister Reg) const;
263 iterator_range<MCRegUnitIterator> regunits(MCRegister Reg) const;
367 const MCRegisterDesc &operator[](MCRegister Reg) const {
368 assert(Reg.id() < NumRegs &&
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUResourceUsageAnalysis.cpp63 const SIInstrInfo &TII, unsigned Reg) { in hasAnyNonFlatUseOfReg() argument
64 for (const MachineOperand &UseOp : MRI.reg_operands(Reg)) { in hasAnyNonFlatUseOfReg()
198 Register Reg = MO.getReg(); in analyzeResourceUsage() local
199 switch (Reg) { in analyzeResourceUsage()
270 if (AMDGPU::SGPR_32RegClass.contains(Reg) || in analyzeResourceUsage()
271 AMDGPU::SGPR_LO16RegClass.contains(Reg) || in analyzeResourceUsage()
272 AMDGPU::SGPR_HI16RegClass.contains(Reg)) { in analyzeResourceUsage()
275 } else if (AMDGPU::VGPR_32RegClass.contains(Reg) || in analyzeResourceUsage()
276 AMDGPU::VGPR_16RegClass.contains(Reg)) { in analyzeResourceUsage()
279 } else if (AMDGPU::AGPR_32RegClass.contains(Reg) || in analyzeResourceUsage()
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H A DAMDGPURegBankLegalizeRules.cpp45 bool matchUniformityAndLLT(Register Reg, UniformityLLTOpPredicateID UniID, in matchUniformityAndLLT() argument
50 return MRI.getType(Reg) == LLT::scalar(1); in matchUniformityAndLLT()
52 return MRI.getType(Reg) == LLT::scalar(16); in matchUniformityAndLLT()
54 return MRI.getType(Reg) == LLT::scalar(32); in matchUniformityAndLLT()
56 return MRI.getType(Reg) == LLT::scalar(64); in matchUniformityAndLLT()
58 return MRI.getType(Reg) == LLT::scalar(128); in matchUniformityAndLLT()
60 return MRI.getType(Reg) == LLT::pointer(0, 64); in matchUniformityAndLLT()
62 return MRI.getType(Reg) == LLT::pointer(1, 64); in matchUniformityAndLLT()
64 return MRI.getType(Reg) == LLT::pointer(3, 32); in matchUniformityAndLLT()
66 return MRI.getType(Reg) == LLT::pointer(4, 64); in matchUniformityAndLLT()
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/freebsd/sys/contrib/dev/acpica/components/hardware/
H A Dhwregs.c168 ACPI_GENERIC_ADDRESS *Reg,
203 ACPI_GENERIC_ADDRESS *Reg, in AcpiHwGetAccessBitWidth() argument
223 if (!Reg->BitOffset && Reg->BitWidth && in AcpiHwGetAccessBitWidth()
224 ACPI_IS_POWER_OF_TWO (Reg->BitWidth) && in AcpiHwGetAccessBitWidth()
225 ACPI_IS_ALIGNED (Reg->BitWidth, 8)) in AcpiHwGetAccessBitWidth()
227 AccessBitWidth = Reg->BitWidth; in AcpiHwGetAccessBitWidth()
229 else if (Reg->AccessWidth) in AcpiHwGetAccessBitWidth()
231 AccessBitWidth = ACPI_ACCESS_BIT_WIDTH (Reg->AccessWidth); in AcpiHwGetAccessBitWidth()
236 Reg->BitOffset + Reg->BitWidth); in AcpiHwGetAccessBitWidth()
252 if (Reg->SpaceId == ACPI_ADR_SPACE_SYSTEM_IO) in AcpiHwGetAccessBitWidth()
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/freebsd/contrib/llvm-project/llvm/lib/DWARFCFIChecker/
H A DRegisters.h27 inline bool isSuperReg(const MCRegisterInfo *MCRI, MCPhysReg Reg) { in isSuperReg() argument
28 return MCRI->superregs(Reg).empty(); in isSuperReg()
35 MCPhysReg Reg = RegClass.getRegister(I); in getSuperRegs() local
36 if (isSuperReg(MCRI, Reg)) in getSuperRegs()
37 SuperRegs.push_back(Reg); in getSuperRegs()
47 for (auto Reg : getSuperRegs(MCRI)) in getTrackingRegs() local
48 if (!MCRI->isArtificial(Reg) && !MCRI->isConstant(Reg)) in getTrackingRegs()
49 TrackingRegs.push_back(Reg); in getTrackingRegs()
53 inline MCPhysReg getSuperReg(const MCRegisterInfo *MCRI, MCPhysReg Reg) { in getSuperReg() argument
54 if (isSuperReg(MCRI, Reg)) in getSuperReg()
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H A DDWARFCFIAnalysis.cpp35 DWARFRegNum Reg; member
38 CFARegOffsetInfo(DWARFRegNum Reg, int64_t Offset) in CFARegOffsetInfo()
39 : Reg(Reg), Offset(Offset) {} in CFARegOffsetInfo()
42 return Reg == RHS.Reg && Offset == RHS.Offset; in operator ==()
57 getUnwindRuleRegSet(const dwarf::UnwindRow &UnwindRow, DWARFRegNum Reg) { in getUnwindRuleRegSet() argument
58 auto MaybeLoc = UnwindRow.getRegisterLocations().getRegisterLocation(Reg); in getUnwindRuleRegSet()
76 return {Reg}; in getUnwindRuleRegSet()
93 DWARFRegNum Reg = MCRI->getDwarfRegNum(LLVMReg, IsEH); in DWARFCFIAnalysis() local
98 State.update(MCCFIInstruction::createSameValue(nullptr, Reg)); in DWARFCFIAnalysis()
118 State.update(MCCFIInstruction::createOffset(nullptr, CFA.Reg, 0)); in DWARFCFIAnalysis()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DMLxExpansionPass.cpp65 bool hasRAWHazard(unsigned Reg, MachineInstr *MI) const;
89 Register Reg = MI->getOperand(1).getReg(); in getAccDefMI() local
90 if (Reg.isPhysical()) in getAccDefMI()
94 MachineInstr *DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
99 Reg = DefMI->getOperand(1).getReg(); in getAccDefMI()
100 if (Reg.isVirtual()) { in getAccDefMI()
101 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
105 Reg = DefMI->getOperand(2).getReg(); in getAccDefMI()
106 if (Reg.isVirtual()) { in getAccDefMI()
107 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
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