Lines Matching refs:Reg
70 unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) { in GetGroup() argument
71 unsigned Node = GroupNodeIndices[Reg]; in GetGroup()
83 for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) { in GetGroupRegs() local
84 if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0)) in GetGroupRegs()
85 Regs.push_back(Reg); in GetGroupRegs()
104 unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg) { in LeaveGroup() argument
110 GroupNodeIndices[Reg] = idx; in LeaveGroup()
114 bool AggressiveAntiDepState::IsLive(unsigned Reg) { in IsLive() argument
117 return((KillIndices[Reg] != ~0u) && (DefIndices[Reg] == ~0u)); in IsLive()
158 unsigned Reg = *AI; in StartBlock() local
159 State->UnionGroups(Reg, 0); in StartBlock()
160 KillIndices[Reg] = BB->size(); in StartBlock()
161 DefIndices[Reg] = ~0u; in StartBlock()
172 unsigned Reg = *I; in StartBlock() local
173 if (!IsReturnBlock && !Pristine.test(Reg)) in StartBlock()
175 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) { in StartBlock()
203 for (unsigned Reg = 1; Reg != TRI->getNumRegs(); ++Reg) { in Observe() local
210 if (State->IsLive(Reg)) { in Observe()
211 LLVM_DEBUG(if (State->GetGroup(Reg) != 0) dbgs() in Observe()
212 << " " << printReg(Reg, TRI) << "=g" << State->GetGroup(Reg) in Observe()
214 State->UnionGroups(Reg, 0); in Observe()
215 } else if ((DefIndices[Reg] < InsertPosIndex) in Observe()
216 && (DefIndices[Reg] >= Count)) { in Observe()
217 DefIndices[Reg] = Count; in Observe()
228 Register Reg = MO.getReg(); in IsImplicitDefUse() local
229 if (Reg == 0) in IsImplicitDefUse()
234 Op = MI.findRegisterUseOperand(Reg, /*TRI=*/nullptr, true); in IsImplicitDefUse()
236 Op = MI.findRegisterDefOperand(Reg, /*TRI=*/nullptr); in IsImplicitDefUse()
248 const Register Reg = MO.getReg(); in GetPassthruRegs() local
249 for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg)) in GetPassthruRegs()
291 void AggressiveAntiDepBreaker::HandleLastUse(unsigned Reg, unsigned KillIdx, in HandleLastUse() argument
304 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) in HandleLastUse()
305 if (TRI->isSuperRegister(Reg, *AI) && State->IsLive(*AI)) { in HandleLastUse()
310 if (!State->IsLive(Reg)) { in HandleLastUse()
311 KillIndices[Reg] = KillIdx; in HandleLastUse()
312 DefIndices[Reg] = ~0u; in HandleLastUse()
313 RegRefs.erase(Reg); in HandleLastUse()
314 State->LeaveGroup(Reg); in HandleLastUse()
316 dbgs() << header << printReg(Reg, TRI); in HandleLastUse()
319 LLVM_DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << tag); in HandleLastUse()
324 for (MCPhysReg SubregReg : TRI->subregs(Reg)) { in HandleLastUse()
331 dbgs() << header << printReg(Reg, TRI); in HandleLastUse()
355 Register Reg = MO.getReg(); in PrescanInstruction() local
356 if (Reg == 0) continue; in PrescanInstruction()
358 HandleLastUse(Reg, Count + 1, "", "\tDead Def: ", "\n"); in PrescanInstruction()
365 Register Reg = MO.getReg(); in PrescanInstruction() local
366 if (Reg == 0) continue; in PrescanInstruction()
368 LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI) << "=g" in PrescanInstruction()
369 << State->GetGroup(Reg)); in PrescanInstruction()
378 LLVM_DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)"); in PrescanInstruction()
379 State->UnionGroups(Reg, 0); in PrescanInstruction()
384 for (MCRegAliasIterator AI(Reg, TRI, false); AI.isValid(); ++AI) { in PrescanInstruction()
387 State->UnionGroups(Reg, AliasReg); in PrescanInstruction()
388 LLVM_DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << "(via " in PrescanInstruction()
398 RegRefs.insert(std::make_pair(Reg, RR)); in PrescanInstruction()
407 Register Reg = MO.getReg(); in PrescanInstruction() local
408 if (Reg == 0) continue; in PrescanInstruction()
410 if (MI.isKill() || (PassthruRegs.count(Reg) != 0)) in PrescanInstruction()
414 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) { in PrescanInstruction()
421 if (TRI->isSuperRegister(Reg, *AI) && State->IsLive(*AI)) in PrescanInstruction()
460 Register Reg = MO.getReg(); in ScanInstruction() local
461 if (Reg == 0) continue; in ScanInstruction()
463 LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI) << "=g" in ScanInstruction()
464 << State->GetGroup(Reg)); in ScanInstruction()
469 HandleLastUse(Reg, Count, "(last-use)"); in ScanInstruction()
472 LLVM_DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)"); in ScanInstruction()
473 State->UnionGroups(Reg, 0); in ScanInstruction()
481 RegRefs.insert(std::make_pair(Reg, RR)); in ScanInstruction()
494 Register Reg = MO.getReg(); in ScanInstruction() local
495 if (Reg == 0) continue; in ScanInstruction()
498 LLVM_DEBUG(dbgs() << "=" << printReg(Reg, TRI)); in ScanInstruction()
499 State->UnionGroups(FirstReg, Reg); in ScanInstruction()
501 LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI)); in ScanInstruction()
502 FirstReg = Reg; in ScanInstruction()
510 BitVector AggressiveAntiDepBreaker::GetRenameRegisters(unsigned Reg) { in GetRenameRegisters() argument
517 for (const auto &Q : make_range(State->GetRegRefs().equal_range(Reg))) { in GetRenameRegisters()
557 for (unsigned Reg : Regs) { in FindSuitableFreeRegisters() local
559 if (RegRefs.count(Reg) > 0) { in FindSuitableFreeRegisters()
560 LLVM_DEBUG(dbgs() << "\t\t" << printReg(Reg, TRI) << ":"); in FindSuitableFreeRegisters()
562 BitVector &BV = RenameRegisterMap[Reg]; in FindSuitableFreeRegisters()
564 BV = GetRenameRegisters(Reg); in FindSuitableFreeRegisters()
576 for (unsigned Reg : Regs) { in FindSuitableFreeRegisters() local
577 if (Reg == SuperReg) continue; in FindSuitableFreeRegisters()
578 bool IsSub = TRI->isSubRegister(SuperReg, Reg); in FindSuitableFreeRegisters()
637 for (unsigned Reg : Regs) { in FindSuitableFreeRegisters() local
639 if (Reg == SuperReg) { in FindSuitableFreeRegisters()
642 unsigned NewSubRegIdx = TRI->getSubRegIndex(SuperReg, Reg); in FindSuitableFreeRegisters()
650 if (!RenameRegisterMap[Reg].test(NewReg)) { in FindSuitableFreeRegisters()
659 if (State->IsLive(NewReg) || (KillIndices[Reg] > DefIndices[NewReg])) { in FindSuitableFreeRegisters()
667 (KillIndices[Reg] > DefIndices[AliasReg])) { in FindSuitableFreeRegisters()
680 for (const auto &Q : make_range(RegRefs.equal_range(Reg))) { in FindSuitableFreeRegisters()
695 for (const auto &Q : make_range(RegRefs.equal_range(Reg))) { in FindSuitableFreeRegisters()
707 RenameMap.insert(std::pair<unsigned, unsigned>(Reg, NewReg)); in FindSuitableFreeRegisters()
772 for (unsigned Reg = 1; Reg < TRI->getNumRegs(); ++Reg) { in BreakAntiDependencies() local
773 if (!State->IsLive(Reg)) in BreakAntiDependencies()
774 LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI)); in BreakAntiDependencies()