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Searched refs:Reduction (Results 1 – 25 of 44) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DExpandVectorPredication.cpp431 Value *Reduction; in expandPredicationInReduction() local
438 Reduction = Builder.CreateAddReduce(RedOp); in expandPredicationInReduction()
439 Reduction = Builder.CreateAdd(Reduction, Start); in expandPredicationInReduction()
442 Reduction = Builder.CreateMulReduce(RedOp); in expandPredicationInReduction()
443 Reduction = Builder.CreateMul(Reduction, Start); in expandPredicationInReduction()
446 Reduction = Builder.CreateAndReduce(RedOp); in expandPredicationInReduction()
447 Reduction = Builder.CreateAnd(Reduction, Start); in expandPredicationInReduction()
450 Reduction = Builder.CreateOrReduce(RedOp); in expandPredicationInReduction()
451 Reduction = Builder.CreateOr(Reduction, Start); in expandPredicationInReduction()
454 Reduction = Builder.CreateXorReduce(RedOp); in expandPredicationInReduction()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMParallelDSP.cpp56 class Reduction;
86 class Reduction { class
94 Reduction() = delete;
96 Reduction (Instruction *Add) : Root(Add) { } in Reduction() function in __anon176cfc890111::Reduction
222 bool Search(Value *V, BasicBlock *BB, Reduction &R);
224 void InsertParallelMACs(Reduction &Reduction);
227 bool CreateParallelPairs(Reduction &R);
428 bool ARMParallelDSP::Search(Value *V, BasicBlock *BB, Reduction &R) { in Search()
525 Reduction R(&I); in MatchSMLAD()
545 bool ARMParallelDSP::CreateParallelPairs(Reduction &R) { in CreateParallelPairs()
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/freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
H A DLoopVectorizationLegality.cpp1181 return (all_of(getReductionVars(), [&](auto &Reduction) -> bool { in canVectorizeFPMath() argument
1182 const RecurrenceDescriptor &RdxDesc = Reduction.second; in canVectorizeFPMath()
1188 return any_of(getReductionVars(), [&](auto &Reduction) -> bool { in isInvariantStoreOfReduction() argument
1189 const RecurrenceDescriptor &RdxDesc = Reduction.second; in isInvariantStoreOfReduction()
1195 return any_of(getReductionVars(), [&](auto &Reduction) -> bool { in isInvariantAddressOfReduction() argument
1196 const RecurrenceDescriptor &RdxDesc = Reduction.second; in isInvariantAddressOfReduction()
1552 for (const auto &Reduction : getReductionVars()) in canFoldTailByMasking() local
1553 ReductionLiveOuts.insert(Reduction.second.getLoopExitInstr()); in canFoldTailByMasking()
H A DLoopVectorize.cpp1336 return (all_of(Legal->getReductionVars(), [&](auto &Reduction) -> bool { in canVectorizeReductions() argument
1337 const RecurrenceDescriptor &RdxDesc = Reduction.second; in canVectorizeReductions()
5043 any_of(Legal->getReductionVars(), [&](auto &Reduction) -> bool { in selectInterleaveCount() argument
5044 const RecurrenceDescriptor &RdxDesc = Reduction.second; in selectInterleaveCount()
5060 any_of(Legal->getReductionVars(), [&](auto &Reduction) -> bool { in selectInterleaveCount() argument
5061 const RecurrenceDescriptor &RdxDesc = Reduction.second; in selectInterleaveCount()
6722 for (const auto &Reduction : Legal->getReductionVars()) { in collectValuesToIgnore() local
6723 const RecurrenceDescriptor &RedDes = Reduction.second; in collectValuesToIgnore()
6737 for (const auto &Reduction : Legal->getReductionVars()) { in collectInLoopReductions() local
6738 PHINode *Phi = Reduction.first; in collectInLoopReductions()
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/freebsd/sys/contrib/device-tree/Bindings/power/avs/
H A Dqcom,cpr.txt1 QCOM CPR (Core Power Reduction)
3 CPR (Core Power Reduction) is a technology to reduce core power on a CPU
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVScheduleV.td20 // Used for widening floating-point Reduction as it doesn't contain MF8.
475 // 14. Vector Reduction Operations
480 // 14.1. Vector Single-Width Integer Reduction Instructions
483 // 14.2. Vector Widening Integer Reduction Instructions
485 // 14.3. Vector Single-Width Floating-Point Reduction Instructions
489 // 14.4. Vector Widening Floating-Point Reduction Instructions
703 // 14. Vector Reduction Operations
704 // 14.1. Vector Single-Width Integer Reduction Instructions
707 // 14.2. Vector Widening Integer Reduction Instructions
710 // 14.3. Vector Single-Width Floating-Point Reduction Instructions
[all …]
H A DRISCVInstrInfoV.td1505 // Vector Single-Width Integer Reduction Instructions
1517 // Vector Widening Integer Reduction Instructions
1530 // Vector Single-Width Floating-Point Reduction Instructions
1545 // Vector Widening Floating-Point Reduction Instructions
H A DRISCVSchedSiFiveP600.td596 // 14. Vector Reduction Operations
1041 // 15. Vector Reduction Operations
/freebsd/usr.sbin/lpr/filters.ru/
H A Dbjc-240.sh.sample55 Reduction=Off
/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A DOpenACCKinds.h254 Reduction, enumerator
404 case OpenACCClauseKind::Reduction: in printOpenACCClauseKind()
H A DOpenACCClauses.def51 VISIT_CLAUSE(Reduction)
H A Darm_mve.td539 multiclass Reduction<Type Accumulator, string basename, list<Type> basetypes,
561 defm vminvq: Reduction<Scalar, "minv", [Vector], 1, (seq (Scalar $ret))>;
562 defm vmaxvq: Reduction<Scalar, "maxv", [Vector], 1, (seq (Scalar $ret))>;
566 defm vminavq: Reduction<UScalar, "minav", [Vector], 0, (seq (UScalar $ret))>;
567 defm vmaxavq: Reduction<UScalar, "maxav", [Vector], 0, (seq (UScalar $ret))>;
571 defm vminnmvq: Reduction<Scalar, "minnmv", [Scalar, Vector]>;
572 defm vmaxnmvq: Reduction<Scalar, "maxnmv", [Scalar, Vector]>;
573 defm vminnmavq: Reduction<Scalar, "minnmav", [Scalar, Vector]>;
574 defm vmaxnmavq: Reduction<Scalar, "maxnmav", [Scalar, Vector]>;
H A Driscv_vector.td2082 // 14. Vector Reduction Operations
2083 // 14.1. Vector Single-Width Integer Reduction Instructions
2096 // 14.2. Vector Widening Integer Reduction Instructions
2097 // Vector Widening Integer Reduction Operations
2105 // 14.3. Vector Single-Width Floating-Point Reduction Instructions
2151 // 14.3. Vector Single-Width Floating-Point Reduction Instructions
2155 // 14.4. Vector Widening Floating-Point Reduction Instructions
2159 // 14.3. Vector Single-Width Floating-Point Reduction Instructions
2163 // 14.4. Vector Widening Floating-Point Reduction Instructions
/freebsd/contrib/llvm-project/clang/include/clang/Sema/
H A DSemaOpenACC.h210 ClauseKind == OpenACCClauseKind::Reduction || in getVarList()
214 if (ClauseKind == OpenACCClauseKind::Reduction) in getVarList()
363 assert(ClauseKind == OpenACCClauseKind::Reduction && in setReductionDetails()
/freebsd/contrib/llvm-project/clang/lib/Sema/
H A DSemaOpenACC.cpp312 case OpenACCClauseKind::Reduction: in doesClauseApplyToDirective()
1385 if (CK != OpenACCClauseKind::Reduction) { in ActOnVar()
1399 (CK != OpenACCClauseKind::Reduction && in ActOnVar()
1409 << (CK != OpenACCClauseKind::Reduction); in ActOnVar()
/freebsd/contrib/llvm-project/lldb/source/Plugins/TraceExporter/docs/
H A Dhtr.rst33 **Basic Super Block Reduction**
/freebsd/contrib/llvm-project/clang/lib/Parse/
H A DParseOpenACC.cpp139 .Case("reduction", OpenACCClauseKind::Reduction) in getOpenACCClauseKind()
523 case OpenACCClauseKind::Reduction: in getClauseParensKind()
941 case OpenACCClauseKind::Reduction: { in ParseOpenACCClauseParams()
/freebsd/contrib/llvm-project/clang/include/clang/AST/
H A DOpenACCClause.h831 : OpenACCClauseWithVarList(OpenACCClauseKind::Reduction, BeginLoc, in OpenACCReductionClause()
841 return C->getClauseKind() == OpenACCClauseKind::Reduction; in classof()
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsdm660-xiaomi-lavender.dts227 * by the Core Power Reduction hardened (CPRh) and the
H A Dsdm670-google-sargo.dts202 * by the Core Power Reduction hardened (CPRh) and the
H A Dsdm630-sony-xperia-nile.dtsi431 * by the Core Power Reduction hardened (CPRh) and the
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedA510.td957 // Reduction, arithmetic, B form
960 // Reduction, arithmetic, H form
963 // Reduction, arithmetic, S form
966 // Reduction, arithmetic, D form
969 // Reduction, logical
H A DAArch64SchedNeoverseV1.td1514 // Reduction, arithmetic, B form
1518 // Reduction, arithmetic, H form
1522 // Reduction, arithmetic, S form
1526 // Reduction, arithmetic, D form
1530 // Reduction, logical
H A DAArch64SchedNeoverseN2.td1875 // Reduction, arithmetic, B form
1878 // Reduction, arithmetic, H form
1881 // Reduction, arithmetic, S form
1884 // Reduction, arithmetic, D form
1887 // Reduction, logical
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsRISCV.td857 // For Reduction ternary operations.
867 // For Reduction ternary operations with mask.
878 // For Reduction ternary operations.
888 // For Reduction ternary operations with mask.

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