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Searched refs:RecVec (Results 1 – 11 of 11) sorted by relevance

/freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenSchedule.cpp258 const RecVec Decls = Records.getAllDerivedDefinitions("STIPredicateDecl"); in checkSTIPredicates()
272 const RecVec Defs = in checkSTIPredicates()
275 RecVec Opcodes = R->getValueAsListOfDefs("Opcodes"); in checkSTIPredicates()
315 RecVec Classes = Def->getValueAsListOfDefs("Classes"); in processSTIPredicate()
321 RecVec Opcodes = EC->getValueAsListOfDefs("Opcodes"); in processSTIPredicate()
346 RecVec Classes = Def->getValueAsListOfDefs("Classes"); in processSTIPredicate()
353 RecVec Opcodes = EC->getValueAsListOfDefs("Opcodes"); in processSTIPredicate()
420 RecVec RV = Records.getAllDerivedDefinitions("STIPredicate"); in collectSTIPredicates()
456 RecVec MCPredicates = Records.getAllDerivedDefinitions("TIIPredicate"); in checkMCInstPredicates()
478 RecVec Units = Records.getAllDerivedDefinitions("RetireControlUnit"); in collectRetireControlUnits()
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H A DCodeGenSchedule.h36 using RecVec = std::vector<Record *>; variable
59 RecVec Aliases;
103 RecVec PredTerm;
146 RecVec InstRWs;
232 RecVec ItinDefList;
236 RecVec ItinRWDefs;
240 RecVec UnsupportedFeaturesDefs;
243 RecVec WriteResDefs;
244 RecVec ReadAdvanceDefs;
247 RecVec ProcResourceDefs;
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H A DPredicateExpander.h55 using RecVec = std::vector<Record *>; variable
76 void expandCheckPseudo(raw_ostream &OS, const RecVec &Opcodes);
77 void expandCheckOpcode(raw_ostream &OS, const RecVec &Opcodes);
78 void expandPredicateSequence(raw_ostream &OS, const RecVec &Sequence,
94 void expandOpcodeSwitchStatement(raw_ostream &OS, const RecVec &Cases,
H A DPredicateExpander.cpp142 const RecVec &Opcodes) { in expandCheckOpcode()
172 const RecVec &Opcodes) { in expandCheckPseudo()
180 const RecVec &Sequence, in expandPredicateSequence()
270 const RecVec &Opcodes = Rec->getValueAsListOfDefs("Opcodes"); in expandOpcodeSwitchCase()
284 const RecVec &Cases, in expandOpcodeSwitchStatement()
464 RecVec Delegates = Fn.getDeclaration()->getValueAsListOfDefs("Delegates"); in expandPrologue()
H A DCodeGenRegisters.cpp776 const SetTheory::RecVec *Elements = RegBank.getSets().expand(R); in CodeGenRegisterClass()
/freebsd/contrib/llvm-project/llvm/include/llvm/TableGen/
H A DSetTheory.h67 using RecVec = std::vector<Record *>;
98 using ExpandMap = std::map<Record *, RecVec>;
140 const RecVec *expand(Record *Set);
/freebsd/contrib/llvm-project/llvm/lib/TableGen/
H A DSetTheory.cpp35 using RecVec = SetTheory::RecVec; typedef
229 if (const RecVec *Result = ST.expand(Rec)) in apply()
284 if (const RecVec *Result = expand(Def->getDef())) in evaluate()
307 const RecVec *SetTheory::expand(Record *Set) { in expand()
322 RecVec &EltVec = Expansions[Set]; in expand()
/freebsd/contrib/llvm-project/llvm/utils/TableGen/
H A DSubtargetEmitter.cpp121 void ExpandProcResources(RecVec &PRVec, std::vector<int64_t> &ReleaseAtCycles,
191 static void printFeatureMask(raw_ostream &OS, RecVec &FeatureList, in printFeatureMask()
287 RecVec ImpliesList = Feature->getValueAsListOfDefs("Implies"); in FeatureKeyValues()
325 RecVec FeatureList = Processor->getValueAsListOfDefs("Features"); in CPUKeyValues()
326 RecVec TuneFeatureList = Processor->getValueAsListOfDefs("TuneFeatures"); in CPUKeyValues()
358 RecVec StageList = ItinData->getValueAsListOfDefs("Stages"); in FormItineraryStageString()
371 RecVec UnitList = Stage->getValueAsListOfDefs("Units"); in FormItineraryStageString()
419 RecVec BypassList = ItinData->getValueAsListOfDefs("Bypasses"); in FormItineraryBypassString()
449 RecVec FUs = ProcModel.ItinsDef->getValueAsListOfDefs("FU"); in EmitStageAndOperandCycleData()
463 RecVec BPs = ProcModel.ItinsDef->getValueAsListOfDefs("BP"); in EmitStageAndOperandCycleData()
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H A DDFAPacketizerEmitter.cpp82 void createScheduleClasses(unsigned ItineraryIdx, const RecVec &Itineraries);
192 const RecVec &Itineraries) { in createScheduleClasses()
H A DInstrInfoEmitter.cpp675 RecVec TIIPredicates = Records.getAllDerivedDefinitions("TIIPredicate"); in emitMCIIHelperMethods()
893 RecVec TIIPredicates = Records.getAllDerivedDefinitions("TIIPredicate"); in emitTIIHelperMethods()
H A DRegisterInfoEmitter.cpp1676 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet); in runTargetDesc()