258   const RecVec Decls = Records.getAllDerivedDefinitions("STIPredicateDecl");  in checkSTIPredicates()
272   const RecVec Defs =  in checkSTIPredicates()
275     RecVec Opcodes = R->getValueAsListOfDefs("Opcodes");  in checkSTIPredicates()
315     RecVec Classes = Def->getValueAsListOfDefs("Classes");  in processSTIPredicate()
321       RecVec Opcodes = EC->getValueAsListOfDefs("Opcodes");  in processSTIPredicate()
346     RecVec Classes = Def->getValueAsListOfDefs("Classes");  in processSTIPredicate()
353       RecVec Opcodes = EC->getValueAsListOfDefs("Opcodes");  in processSTIPredicate()
420   RecVec RV = Records.getAllDerivedDefinitions("STIPredicate");  in collectSTIPredicates()
456   RecVec MCPredicates = Records.getAllDerivedDefinitions("TIIPredicate");  in checkMCInstPredicates()
478   RecVec Units = Records.getAllDerivedDefinitions("RetireControlUnit");  in collectRetireControlUnits()
493   RecVec Queues = Records.getAllDerivedDefinitions("MemoryQueue");  in collectLoadStoreQueueInfo()
535   RecVec ProcRecords = Records.getAllDerivedDefinitions("Processor");  in collectProcModels()
585 static void scanSchedRW(Record *RWDef, RecVec &RWDefs,  in scanSchedRW()
592     RecVec Seq = RWDef->getValueAsListOfDefs("Writes");  in scanSchedRW()
597     RecVec Vars = RWDef->getValueAsListOfDefs("Variants");  in scanSchedRW()
600       RecVec Selected = Variant->getValueAsListOfDefs("Selected");  in scanSchedRW()
617   RecVec SWDefs, SRDefs;  in collectSchedRW()
622     RecVec RWs = SchedDef->getValueAsListOfDefs("SchedRW");  in collectSchedRW()
633   RecVec InstRWDefs = Records.getAllDerivedDefinitions("InstRW");  in collectSchedRW()
636     RecVec RWDefs = InstRWDef->getValueAsListOfDefs("OperandReadWrites");  in collectSchedRW()
647   RecVec ItinRWDefs = Records.getAllDerivedDefinitions("ItinRW");  in collectSchedRW()
650     RecVec RWDefs = ItinRWDef->getValueAsListOfDefs("OperandReadWrites");  in collectSchedRW()
662   RecVec AliasDefs = Records.getAllDerivedDefinitions("SchedAlias");  in collectSchedRW()
718       } RecVec RWDefs = Records.getAllDerivedDefinitions("SchedReadWrite");  in collectSchedRW()
749 static void splitSchedReadWrites(const RecVec &RWDefs, RecVec &WriteDefs,  in splitSchedReadWrites()
750                                  RecVec &ReadDefs) {  in splitSchedReadWrites()
762 void CodeGenSchedModels::findRWs(const RecVec &RWDefs, IdxVec &Writes,  in findRWs()
764   RecVec WriteDefs;  in findRWs()
765   RecVec ReadDefs;  in findRWs()
772 void CodeGenSchedModels::findRWs(const RecVec &RWDefs, IdxVec &RWs,  in findRWs()
890   RecVec InstRWDefs = Records.getAllDerivedDefinitions("InstRW");  in collectSchedClasses()
939     const RecVec &RWDefs = SchedClasses[SCIdx].InstRWs;  in collectSchedClasses()
996 std::string CodeGenSchedModels::createSchedClassName(const RecVec &InstDefs) {  in createSchedClassName()
1051   const RecVec *InstDefs = Sets.expand(InstRWDef);  in createInstRWClass()
1070       const RecVec &RWDefs = SchedClasses[OldSCIdx].InstRWs;  in createInstRWClass()
1072         const RecVec *OrigInstDefs = Sets.expand(RWDefs[0]);  in createInstRWClass()
1157     RecVec ItinRecords = ProcModel.ItinsDef->getValueAsListOfDefs("IID");  in collectProcItins()
1197   RecVec ItinRWDefs = Records.getAllDerivedDefinitions("ItinRW");  in collectProcItinRW()
1252       RecVec Matched = Rec->getValueAsListOfDefs("MatchedItinClasses");  in inferFromItinClass()
1272     const RecVec *InstDefs = Sets.expand(Rec);  in inferFromInstRWs()
1376     RecVec Variants = SchedRW.TheDef->getValueAsListOfDefs("Variants");  in mutuallyExclusive()
1442       const RecVec VarDefs = SchedRW.TheDef->getValueAsListOfDefs("Variants");  in getIntersectingVariants()
1474       const RecVec VarDefs = AliasRW.TheDef->getValueAsListOfDefs("Variants");  in getIntersectingVariants()
1523     RecVec SelectedDefs = VInfo.VarOrSeqDef->getValueAsListOfDefs("Selected");  in pushVariant()
1653 static void dumpRecVec(const RecVec &RV) {  in dumpRecVec()
1662                            const RecVec &Preds) {  in dumpTransition()
1699     RecVec Preds;  in inferFromTransitions()
1789 bool CodeGenSchedModels::hasSuperGroup(RecVec &SubUnits, CodeGenProcModel &PM) {  in hasSuperGroup()
1793     RecVec SuperUnits = ProcResourceDef->getValueAsListOfDefs("Resources");  in hasSuperGroup()
1811     RecVec CheckUnits =  in verifyProcResourceGroups()
1816       RecVec OtherUnits =  in verifyProcResourceGroups()
1836   RecVec RegisterFileDefs = Records.getAllDerivedDefinitions("RegisterFile");  in collectRegisterFiles()
1858     RecVec RegisterClasses = RF->getValueAsListOfDefs("RegClasses");  in collectRegisterFiles()
1903   RecVec WRDefs = Records.getAllDerivedDefinitions("WriteRes");  in collectProcResources()
1908   RecVec SWRDefs = Records.getAllDerivedDefinitions("SchedWriteRes");  in collectProcResources()
1913   RecVec RADefs = Records.getAllDerivedDefinitions("ReadAdvance");  in collectProcResources()
1918   RecVec SRADefs = Records.getAllDerivedDefinitions("SchedReadAdvance");  in collectProcResources()
1927   RecVec ProcResGroups = Records.getAllDerivedDefinitions("ProcResGroup");  in collectProcResources()
2007       const RecVec &InstRWs = SC.InstRWs;  in checkCompleteness()
2044       RecVec Matched = (*II)->getValueAsListOfDefs("MatchedItinClasses");  in collectItinProcResources()
2166   RecVec &WRDefs = ProcModels[PIdx].WriteResDefs;  in addWriteRes()
2172   RecVec ProcResDefs = ProcWriteResDef->getValueAsListOfDefs("ProcResources");  in addWriteRes()
2190   RecVec &RADefs = ProcModels[PIdx].ReadAdvanceDefs;  in addReadAdvance()
2219     RecVec ValidWrites = RADef->getValueAsListOfDefs("ValidWrites");  in hasReadOfWrite()