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Searched refs:ReadAdvance (Results 1 – 25 of 82) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVSchedTTAscalonD8.td217 def : ReadAdvance<ReadJmp, 0>;
218 def : ReadAdvance<ReadJalr, 0>;
219 def : ReadAdvance<ReadCSR, 0>;
220 def : ReadAdvance<ReadStoreData, 0>;
221 def : ReadAdvance<ReadMemBase, 0>;
222 def : ReadAdvance<ReadIALU, 0>;
223 def : ReadAdvance<ReadIALU32, 0>;
224 def : ReadAdvance<ReadShiftImm, 0>;
225 def : ReadAdvance<ReadShiftImm32, 0>;
226 def : ReadAdvance<ReadShiftReg, 0>;
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H A DRISCVSchedAndes45.td234 def : ReadAdvance<ReadIALU, 0>;
235 def : ReadAdvance<ReadIALU32, 0>;
236 def : ReadAdvance<ReadShiftImm, 0>;
237 def : ReadAdvance<ReadShiftImm32, 0>;
238 def : ReadAdvance<ReadShiftReg, 0>;
239 def : ReadAdvance<ReadShiftReg32, 0>;
240 def : ReadAdvance<ReadSFBJmp, 0>;
241 def : ReadAdvance<ReadSFBALU, 0>;
242 def : ReadAdvance<ReadJalr, 0>;
243 def : ReadAdvance<ReadJmp, 0>;
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H A DRISCVSchedGenericOOO.td361 def : ReadAdvance<ReadJmp, 0>;
362 def : ReadAdvance<ReadJalr, 0>;
363 def : ReadAdvance<ReadCSR, 0>;
364 def : ReadAdvance<ReadStoreData, 0>;
365 def : ReadAdvance<ReadMemBase, 0>;
366 def : ReadAdvance<ReadIALU, 0>;
367 def : ReadAdvance<ReadIALU32, 0>;
368 def : ReadAdvance<ReadShiftImm, 0>;
369 def : ReadAdvance<ReadShiftImm32, 0>;
370 def : ReadAdvance<ReadShiftReg, 0>;
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H A DRISCVSchedSiFiveP500.td250 def : ReadAdvance<ReadJmp, 0>;
251 def : ReadAdvance<ReadJalr, 0>;
252 def : ReadAdvance<ReadCSR, 0>;
253 def : ReadAdvance<ReadStoreData, 0>;
254 def : ReadAdvance<ReadMemBase, 0>;
255 def : ReadAdvance<ReadIALU, 0>;
256 def : ReadAdvance<ReadIALU32, 0>;
257 def : ReadAdvance<ReadShiftImm, 0>;
258 def : ReadAdvance<ReadShiftImm32, 0>;
259 def : ReadAdvance<ReadShiftReg, 0>;
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H A DRISCVSchedSpacemitX60.td241 def : ReadAdvance<ReadJmp, 0>;
242 def : ReadAdvance<ReadJalr, 0>;
243 def : ReadAdvance<ReadCSR, 0>;
244 def : ReadAdvance<ReadStoreData, 0>;
245 def : ReadAdvance<ReadMemBase, 0>;
246 def : ReadAdvance<ReadIALU, 0>;
247 def : ReadAdvance<ReadIALU32, 0>;
248 def : ReadAdvance<ReadShiftImm, 0>;
249 def : ReadAdvance<ReadShiftImm32, 0>;
250 def : ReadAdvance<ReadShiftReg, 0>;
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H A DRISCVSchedMIPSP8700.td188 def : ReadAdvance<ReadIALU, 0>;
189 def : ReadAdvance<ReadIALU32, 0>;
190 def : ReadAdvance<ReadShiftImm, 0>;
191 def : ReadAdvance<ReadShiftImm32, 0>;
192 def : ReadAdvance<ReadShiftReg, 0>;
193 def : ReadAdvance<ReadShiftReg32, 0>;
194 def : ReadAdvance<ReadSHXADD, 0>;
195 def : ReadAdvance<ReadSHXADD32, 0>;
196 def : ReadAdvance<ReadRotateReg, 0>;
197 def : ReadAdvance<ReadRotateImm, 0>;
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H A DRISCVSchedSyntacoreSCR7.td257 def : ReadAdvance<ReadJmp, 0>;
258 def : ReadAdvance<ReadJalr, 0>;
259 def : ReadAdvance<ReadCSR, 0>;
260 def : ReadAdvance<ReadStoreData, 0>;
261 def : ReadAdvance<ReadMemBase, 0>;
262 def : ReadAdvance<ReadIALU, 0>;
263 def : ReadAdvance<ReadIALU32, 0>;
264 def : ReadAdvance<ReadShiftImm, 0>;
265 def : ReadAdvance<ReadShiftImm32, 0>;
266 def : ReadAdvance<ReadShiftReg, 0>;
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H A DRISCVSchedRocket.td189 def : ReadAdvance<ReadJmp, 0>;
190 def : ReadAdvance<ReadJalr, 0>;
191 def : ReadAdvance<ReadCSR, 0>;
192 def : ReadAdvance<ReadStoreData, 0>;
193 def : ReadAdvance<ReadMemBase, 0>;
194 def : ReadAdvance<ReadIALU, 0>;
195 def : ReadAdvance<ReadIALU32, 0>;
196 def : ReadAdvance<ReadShiftImm, 0>;
197 def : ReadAdvance<ReadShiftImm32, 0>;
198 def : ReadAdvance<ReadShiftReg, 0>;
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H A DRISCVSchedXiangShanNanHu.td212 …: ReadAdvance<read, 1, [WriteLDB, WriteLDH, WriteLDW, WriteLDD, WriteAtomicW, WriteAtomicD, WriteA…
214 def : ReadAdvance<ReadJmp, 0>;
215 def : ReadAdvance<ReadJalr, 0>;
216 def : ReadAdvance<ReadCSR, 0>;
217 def : ReadAdvance<ReadStoreData, 0>;
218 def : ReadAdvance<ReadMemBase, 0>;
225 def : ReadAdvance<ReadIDiv, 0>;
226 def : ReadAdvance<ReadIDiv32, 0>;
227 def : ReadAdvance<ReadIRem, 0>;
228 def : ReadAdvance<ReadIRem32, 0>;
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H A DRISCVSchedSyntacoreSCR345.td207 def : ReadAdvance<ReadJmp, 0>;
208 def : ReadAdvance<ReadJalr, 0>;
209 def : ReadAdvance<ReadCSR, 0>;
210 def : ReadAdvance<ReadStoreData, 0>;
211 def : ReadAdvance<ReadMemBase, 0>;
212 def : ReadAdvance<ReadIALU, 0>;
213 def : ReadAdvance<ReadIALU32, 0>;
214 def : ReadAdvance<ReadShiftImm, 0>;
215 def : ReadAdvance<ReadShiftImm32, 0>;
216 def : ReadAdvance<ReadShiftReg, 0>;
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H A DRISCVSchedule.td273 def : ReadAdvance<ReadFAdd16, 0>;
274 def : ReadAdvance<ReadFClass16, 0>;
275 def : ReadAdvance<ReadFCvtI64ToF16, 0>;
276 def : ReadAdvance<ReadFCvtI32ToF16, 0>;
277 def : ReadAdvance<ReadFCvtF16ToI64, 0>;
278 def : ReadAdvance<ReadFCvtF16ToI32, 0>;
279 def : ReadAdvance<ReadFDiv16, 0>;
280 def : ReadAdvance<ReadFCmp16, 0>;
281 def : ReadAdvance<ReadFMA16, 0>;
282 def : ReadAdvance<ReadFMA16Addend, 0>;
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H A DRISCVScheduleZb.td92 def : ReadAdvance<ReadSHXADD, 0>;
93 def : ReadAdvance<ReadSHXADD32, 0>;
113 def : ReadAdvance<ReadRotateImm, 0>;
114 def : ReadAdvance<ReadRotateImm32, 0>;
115 def : ReadAdvance<ReadRotateReg, 0>;
116 def : ReadAdvance<ReadRotateReg32, 0>;
117 def : ReadAdvance<ReadCLZ, 0>;
118 def : ReadAdvance<ReadCLZ32, 0>;
119 def : ReadAdvance<ReadCTZ, 0>;
120 def : ReadAdvance<ReadCTZ32, 0>;
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H A DRISCVSchedSiFiveP800.td862 def : ReadAdvance<ReadJmp, 0>;
863 def : ReadAdvance<ReadJalr, 0>;
864 def : ReadAdvance<ReadCSR, 0>;
865 def : ReadAdvance<ReadStoreData, 0>;
866 def : ReadAdvance<ReadMemBase, 0>;
867 def : ReadAdvance<ReadIALU, 0>;
868 def : ReadAdvance<ReadIALU32, 0>;
869 def : ReadAdvance<ReadShiftImm, 0>;
870 def : ReadAdvance<ReadShiftImm32, 0>;
871 def : ReadAdvance<ReadShiftReg, 0>;
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H A DRISCVSchedSiFiveP400.td920 def : ReadAdvance<ReadJmp, 0>;
921 def : ReadAdvance<ReadJalr, 0>;
922 def : ReadAdvance<ReadCSR, 0>;
923 def : ReadAdvance<ReadStoreData, 0>;
924 def : ReadAdvance<ReadMemBase, 0>;
925 def : ReadAdvance<ReadIALU, 0>;
926 def : ReadAdvance<ReadIALU32, 0>;
927 def : ReadAdvance<ReadShiftImm, 0>;
928 def : ReadAdvance<ReadShiftImm32, 0>;
929 def : ReadAdvance<ReadShiftReg, 0>;
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H A DRISCVSchedSyntacoreSCR1.td87 def : ReadAdvance<ReadJmp, 0>;
88 def : ReadAdvance<ReadJalr, 0>;
89 def : ReadAdvance<ReadCSR, 0>;
90 def : ReadAdvance<ReadStoreData, 0>;
91 def : ReadAdvance<ReadMemBase, 0>;
92 def : ReadAdvance<ReadIALU, 0>;
93 def : ReadAdvance<ReadIALU32, 0>;
94 def : ReadAdvance<ReadShiftImm, 0>;
95 def : ReadAdvance<ReadShiftImm32, 0>;
96 def : ReadAdvance<ReadShiftReg, 0>;
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H A DRISCVSchedSiFiveP600.td1176 def : ReadAdvance<ReadJmp, 0>;
1177 def : ReadAdvance<ReadJalr, 0>;
1178 def : ReadAdvance<ReadCSR, 0>;
1179 def : ReadAdvance<ReadStoreData, 0>;
1180 def : ReadAdvance<ReadMemBase, 0>;
1181 def : ReadAdvance<ReadIALU, 0>;
1182 def : ReadAdvance<ReadIALU32, 0>;
1183 def : ReadAdvance<ReadShiftImm, 0>;
1184 def : ReadAdvance<ReadShiftImm32, 0>;
1185 def : ReadAdvance<ReadShiftReg, 0>;
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H A DRISCVSchedSiFive7.td193 : ReadAdvance<read, cycles, [WriteIALU, WriteIALU32,
1113 def : ReadAdvance<ReadCSR, 0>;
1115 def : ReadAdvance<ReadMemBase, 0>;
1122 def : ReadAdvance<ReadIDiv, 0>;
1123 def : ReadAdvance<ReadIDiv32, 0>;
1124 def : ReadAdvance<ReadIRem, 0>;
1125 def : ReadAdvance<ReadIRem32, 0>;
1126 def : ReadAdvance<ReadIMul, 0>;
1127 def : ReadAdvance<ReadIMul32, 0>;
1128 def : ReadAdvance<ReadAtomicWA, 0>;
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H A DRISCVScheduleV.td117 // ReadAdvance for each (name, LMUL) pair and for each LMUL in each of the
143 def : ReadAdvance<!cast<SchedRead>(name # "_WorstCase"), val, writes>;
146 def : ReadAdvance<!cast<SchedRead>(name # "_" # mx), val, writes>;
151 // ReadAdvance for each (name, LMUL, SEW) tuple for each LMUL in each of the
185 def : ReadAdvance<!cast<SchedRead>(name # "_WorstCase"), val, writes>;
189 def : ReadAdvance<!cast<SchedRead>(name # "_" # mx # "_E" # sew), val, writes>;
196 // by the ReadAdvance. For example:
979 def : ReadAdvance<ReadVSETVLI, 0>;
980 def : ReadAdvance<ReadVSETVL, 0>;
983 def : ReadAdvance<ReadVLDX, 0>;
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedFalkor.td106 // These ReadAdvance entries are not used in the Falkor sched model.
107 def : ReadAdvance<ReadI, 0>;
108 def : ReadAdvance<ReadISReg, 0>;
109 def : ReadAdvance<ReadIEReg, 0>;
110 def : ReadAdvance<ReadIM, 0>;
111 def : ReadAdvance<ReadIMA, 0>;
112 def : ReadAdvance<ReadID, 0>;
113 def : ReadAdvance<ReadExtrHi, 0>;
114 def : ReadAdvance<ReadAdrBase, 0>;
115 def : ReadAdvance<ReadVL
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H A DAArch64SchedKryo.td113 def : ReadAdvance<ReadI, 0>;
114 def : ReadAdvance<ReadISReg, 0>;
115 def : ReadAdvance<ReadIEReg, 0>;
116 def : ReadAdvance<ReadIM, 0>;
117 def : ReadAdvance<ReadIMA, 0>;
118 def : ReadAdvance<ReadID, 0>;
119 def : ReadAdvance<ReadExtrHi, 0>;
120 def : ReadAdvance<ReadAdrBase, 0>;
121 def : ReadAdvance<ReadVLD, 0>;
122 def : ReadAdvance<ReadS
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H A DAArch64SchedThunderX.td194 def : ReadAdvance<ReadExtrHi, 1>;
195 def : ReadAdvance<ReadAdrBase, 2>;
196 def : ReadAdvance<ReadVLD, 2>;
197 def : ReadAdvance<ReadST, 2>;
203 // ReadAdvance applies to Extended registers as well, even though there is
205 def : ReadAdvance<ReadI, 2, [WriteImm, WriteI,
229 def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
233 def : ReadAdvance<ReadIMA, 2, [WriteImm, WriteI,
239 def : ReadAdvance<ReadID, 1, [WriteImm, WriteI,
H A DAArch64SchedA53.td152 def : ReadAdvance<ReadExtrHi, 0>;
153 def : ReadAdvance<ReadAdrBase, 0>;
154 def : ReadAdvance<ReadST, 0>;
155 def : ReadAdvance<ReadVLD, 0>;
160 // ReadAdvance applies to Extended registers as well, even though there is
162 def : ReadAdvance<ReadI, 2, [WriteImm,WriteI,
186 def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
190 def : ReadAdvance<ReadIMA, 2, [WriteImm,WriteI,
196 def : ReadAdvance<ReadID, 1, [WriteImm,WriteI,
/freebsd/contrib/llvm-project/llvm/lib/MCA/HardwareUnits/
H A DRegisterFile.cpp532 int ReadAdvance = STI.getReadAdvanceCycles(SC, RD.UseIndex, WriteResID); in collectWrites() local
533 if (ReadAdvance < 0) { in collectWrites()
535 if (Elapsed < static_cast<unsigned>(-ReadAdvance)) in collectWrites()
547 int ReadAdvance = STI.getReadAdvanceCycles(SC, RD.UseIndex, WriteResID); in collectWrites() local
548 if (ReadAdvance < 0) { in collectWrites()
550 if (Elapsed < static_cast<unsigned>(-ReadAdvance)) in collectWrites()
590 int ReadAdvance = STI.getReadAdvanceCycles(SC, RD.UseIndex, WriteResID); in checkRAWHazards() local
601 int CyclesLeft = WS->getCyclesLeft() - ReadAdvance; in checkRAWHazards()
651 int ReadAdvance = STI.getReadAdvanceCycles(SC, RD.UseIndex, WriteResID); in addRegisterRead() local
652 WS.addUser(WR.getSourceIndex(), &RS, ReadAdvance); in addRegisterRead()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleM4.td100 def : ReadAdvance<ReadALU, 0>;
101 def : ReadAdvance<ReadALUsr, 0>;
102 def : ReadAdvance<ReadMUL, 0>;
103 def : ReadAdvance<ReadMAC, 0>;
134 def : ReadAdvance<ReadFPMUL, 0>;
135 def : ReadAdvance<ReadFPMAC, 0>;
/freebsd/contrib/llvm-project/llvm/lib/MCA/
H A DInstruction.cpp72 void WriteState::addUser(unsigned IID, ReadState *User, int ReadAdvance) { in addUser() argument
77 unsigned ReadCycles = std::max(0, CyclesLeft - ReadAdvance); in addUser()
82 Users.emplace_back(User, ReadAdvance); in addUser()

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