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Searched refs:ReadAdvance (Results 1 – 25 of 69) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVSchedSiFiveP400.td258 def : ReadAdvance<ReadJmp, 0>;
259 def : ReadAdvance<ReadJalr, 0>;
260 def : ReadAdvance<ReadCSR, 0>;
261 def : ReadAdvance<ReadStoreData, 0>;
262 def : ReadAdvance<ReadMemBase, 0>;
263 def : ReadAdvance<ReadIALU, 0>;
264 def : ReadAdvance<ReadIALU32, 0>;
265 def : ReadAdvance<ReadShiftImm, 0>;
266 def : ReadAdvance<ReadShiftImm32, 0>;
267 def : ReadAdvance<ReadShiftReg, 0>;
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H A DRISCVSchedRocket.td189 def : ReadAdvance<ReadJmp, 0>;
190 def : ReadAdvance<ReadJalr, 0>;
191 def : ReadAdvance<ReadCSR, 0>;
192 def : ReadAdvance<ReadStoreData, 0>;
193 def : ReadAdvance<ReadMemBase, 0>;
194 def : ReadAdvance<ReadIALU, 0>;
195 def : ReadAdvance<ReadIALU32, 0>;
196 def : ReadAdvance<ReadShiftImm, 0>;
197 def : ReadAdvance<ReadShiftImm32, 0>;
198 def : ReadAdvance<ReadShiftReg, 0>;
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H A DRISCVSchedXiangShanNanHu.td212 …: ReadAdvance<read, 1, [WriteLDB, WriteLDH, WriteLDW, WriteLDD, WriteAtomicW, WriteAtomicD, WriteA…
214 def : ReadAdvance<ReadJmp, 0>;
215 def : ReadAdvance<ReadJalr, 0>;
216 def : ReadAdvance<ReadCSR, 0>;
217 def : ReadAdvance<ReadStoreData, 0>;
218 def : ReadAdvance<ReadMemBase, 0>;
225 def : ReadAdvance<ReadIDiv, 0>;
226 def : ReadAdvance<ReadIDiv32, 0>;
227 def : ReadAdvance<ReadIRem, 0>;
228 def : ReadAdvance<ReadIRem32, 0>;
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H A DRISCVSchedule.td238 def : ReadAdvance<ReadFAdd16, 0>;
239 def : ReadAdvance<ReadFClass16, 0>;
240 def : ReadAdvance<ReadFCvtF16ToF64, 0>;
241 def : ReadAdvance<ReadFCvtF64ToF16, 0>;
242 def : ReadAdvance<ReadFCvtI64ToF16, 0>;
243 def : ReadAdvance<ReadFCvtF32ToF16, 0>;
244 def : ReadAdvance<ReadFCvtI32ToF16, 0>;
245 def : ReadAdvance<ReadFCvtF16ToI64, 0>;
246 def : ReadAdvance<ReadFCvtF16ToF32, 0>;
247 def : ReadAdvance<ReadFCvtF16ToI32, 0>;
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H A DRISCVSchedSyntacoreSCR3.td118 def : ReadAdvance<ReadJmp, 0>;
119 def : ReadAdvance<ReadJalr, 0>;
120 def : ReadAdvance<ReadCSR, 0>;
121 def : ReadAdvance<ReadStoreData, 0>;
122 def : ReadAdvance<ReadMemBase, 0>;
123 def : ReadAdvance<ReadIALU, 0>;
124 def : ReadAdvance<ReadIALU32, 0>;
125 def : ReadAdvance<ReadShiftImm, 0>;
126 def : ReadAdvance<ReadShiftImm32, 0>;
127 def : ReadAdvance<ReadShiftReg, 0>;
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H A DRISCVScheduleZb.td92 def : ReadAdvance<ReadSHXADD, 0>;
93 def : ReadAdvance<ReadSHXADD32, 0>;
113 def : ReadAdvance<ReadRotateImm, 0>;
114 def : ReadAdvance<ReadRotateImm32, 0>;
115 def : ReadAdvance<ReadRotateReg, 0>;
116 def : ReadAdvance<ReadRotateReg32, 0>;
117 def : ReadAdvance<ReadCLZ, 0>;
118 def : ReadAdvance<ReadCLZ32, 0>;
119 def : ReadAdvance<ReadCTZ, 0>;
120 def : ReadAdvance<ReadCTZ32, 0>;
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H A DRISCVSchedSiFiveP600.td820 def : ReadAdvance<ReadJmp, 0>;
821 def : ReadAdvance<ReadJalr, 0>;
822 def : ReadAdvance<ReadCSR, 0>;
823 def : ReadAdvance<ReadStoreData, 0>;
824 def : ReadAdvance<ReadMemBase, 0>;
825 def : ReadAdvance<ReadIALU, 0>;
826 def : ReadAdvance<ReadIALU32, 0>;
827 def : ReadAdvance<ReadShiftImm, 0>;
828 def : ReadAdvance<ReadShiftImm32, 0>;
829 def : ReadAdvance<ReadShiftReg, 0>;
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H A DRISCVSchedSyntacoreSCR1.td87 def : ReadAdvance<ReadJmp, 0>;
88 def : ReadAdvance<ReadJalr, 0>;
89 def : ReadAdvance<ReadCSR, 0>;
90 def : ReadAdvance<ReadStoreData, 0>;
91 def : ReadAdvance<ReadMemBase, 0>;
92 def : ReadAdvance<ReadIALU, 0>;
93 def : ReadAdvance<ReadIALU32, 0>;
94 def : ReadAdvance<ReadShiftImm, 0>;
95 def : ReadAdvance<ReadShiftImm32, 0>;
96 def : ReadAdvance<ReadShiftReg, 0>;
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H A DRISCVSchedSiFive7.td179 : ReadAdvance<read, cycles, [WriteIALU, WriteIALU32,
1019 def : ReadAdvance<ReadCSR, 0>;
1021 def : ReadAdvance<ReadMemBase, 0>;
1028 def : ReadAdvance<ReadIDiv, 0>;
1029 def : ReadAdvance<ReadIDiv32, 0>;
1030 def : ReadAdvance<ReadIRem, 0>;
1031 def : ReadAdvance<ReadIRem32, 0>;
1032 def : ReadAdvance<ReadIMul, 0>;
1033 def : ReadAdvance<ReadIMul32, 0>;
1034 def : ReadAdvance<ReadAtomicWA, 0>;
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H A DRISCVScheduleV.td117 // ReadAdvance for each (name, LMUL) pair and for each LMUL in each of the
143 def : ReadAdvance<!cast<SchedRead>(name # "_WorstCase"), val, writes>;
146 def : ReadAdvance<!cast<SchedRead>(name # "_" # mx), val, writes>;
151 // ReadAdvance for each (name, LMUL, SEW) tuple for each LMUL in each of the
185 def : ReadAdvance<!cast<SchedRead>(name # "_WorstCase"), val, writes>;
189 def : ReadAdvance<!cast<SchedRead>(name # "_" # mx # "_E" # sew), val, writes>;
196 // by the ReadAdvance. For example:
973 def : ReadAdvance<ReadVSETVLI, 0>;
974 def : ReadAdvance<ReadVSETVL, 0>;
977 def : ReadAdvance<ReadVLDX, 0>;
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedFalkor.td106 // These ReadAdvance entries are not used in the Falkor sched model.
107 def : ReadAdvance<ReadI, 0>;
108 def : ReadAdvance<ReadISReg, 0>;
109 def : ReadAdvance<ReadIEReg, 0>;
110 def : ReadAdvance<ReadIM, 0>;
111 def : ReadAdvance<ReadIMA, 0>;
112 def : ReadAdvance<ReadID, 0>;
113 def : ReadAdvance<ReadExtrHi, 0>;
114 def : ReadAdvance<ReadAdrBase, 0>;
115 def : ReadAdvance<ReadVL
[all...]
H A DAArch64SchedKryo.td113 def : ReadAdvance<ReadI, 0>;
114 def : ReadAdvance<ReadISReg, 0>;
115 def : ReadAdvance<ReadIEReg, 0>;
116 def : ReadAdvance<ReadIM, 0>;
117 def : ReadAdvance<ReadIMA, 0>;
118 def : ReadAdvance<ReadID, 0>;
119 def : ReadAdvance<ReadExtrHi, 0>;
120 def : ReadAdvance<ReadAdrBase, 0>;
121 def : ReadAdvance<ReadVLD, 0>;
122 def : ReadAdvance<ReadS
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H A DAArch64SchedThunderX.td194 def : ReadAdvance<ReadExtrHi, 1>;
195 def : ReadAdvance<ReadAdrBase, 2>;
196 def : ReadAdvance<ReadVLD, 2>;
197 def : ReadAdvance<ReadST, 2>;
203 // ReadAdvance applies to Extended registers as well, even though there is
205 def : ReadAdvance<ReadI, 2, [WriteImm, WriteI,
229 def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
233 def : ReadAdvance<ReadIMA, 2, [WriteImm, WriteI,
239 def : ReadAdvance<ReadID, 1, [WriteImm, WriteI,
H A DAArch64SchedA53.td152 def : ReadAdvance<ReadExtrHi, 0>;
153 def : ReadAdvance<ReadAdrBase, 0>;
154 def : ReadAdvance<ReadST, 0>;
155 def : ReadAdvance<ReadVLD, 0>;
160 // ReadAdvance applies to Extended registers as well, even though there is
162 def : ReadAdvance<ReadI, 2, [WriteImm,WriteI,
186 def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
190 def : ReadAdvance<ReadIMA, 2, [WriteImm,WriteI,
196 def : ReadAdvance<ReadID, 1, [WriteImm,WriteI,
H A DAArch64SchedA55.td210 def : ReadAdvance<ReadVLD, 0>;
211 def : ReadAdvance<ReadExtrHi, 1>;
212 def : ReadAdvance<ReadAdrBase, 1>;
213 def : ReadAdvance<ReadST, 1>;
219 def : ReadAdvance<ReadI, 2, [WriteImm,WriteI,
243 def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
247 def : ReadAdvance<ReadIMA, 2, [WriteImm,WriteI,
253 def : ReadAdvance<ReadID, 1, [WriteImm,WriteI,
H A DAArch64SchedExynosM3.td272 def : ReadAdvance<ReadI, 0>;
273 def : ReadAdvance<ReadISReg, 0>;
274 def : ReadAdvance<ReadIEReg, 0>;
275 def : ReadAdvance<ReadIM, 0>;
277 def : ReadAdvance<ReadIMA, 3, [WriteIM32, WriteIM64]>;
278 def : ReadAdvance<ReadID, 0>;
279 def : ReadAdvance<ReadExtrHi, 0>;
280 def : ReadAdvance<ReadAdrBase, 0>;
281 def : ReadAdvance<ReadVLD, 0>;
282 def : ReadAdvance<ReadS
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H A DAArch64SchedTSV110.td113 def : ReadAdvance<ReadI, 0>;
114 def : ReadAdvance<ReadISReg, 0>;
115 def : ReadAdvance<ReadIEReg, 0>;
116 def : ReadAdvance<ReadIM, 0>;
117 def : ReadAdvance<ReadIMA, 2, [WriteIM32, WriteIM64]>;
118 def : ReadAdvance<ReadID, 0>;
119 def : ReadAdvance<ReadExtrHi, 0>;
120 def : ReadAdvance<ReadAdrBase, 0>;
121 def : ReadAdvance<ReadVLD, 0>;
122 def : ReadAdvance<ReadST, 0>;
H A DAArch64SchedCyclone.td187 def : ReadAdvance<ReadExtrHi, 1>;
262 def : ReadAdvance<ReadST, 0>;
638 def : ReadAdvance<ReadVLD, 5>;
868 def : ReadAdvance<ReadI, 0>;
869 def : ReadAdvance<ReadISReg, 0>;
870 def : ReadAdvance<ReadIEReg, 0>;
871 def : ReadAdvance<ReadIM, 0>;
872 def : ReadAdvance<ReadIMA, 0>;
873 def : ReadAdvance<ReadID, 0>;
H A DAArch64SchedA57.td114 def : ReadAdvance<ReadI, 0>;
115 def : ReadAdvance<ReadISReg, 0>;
116 def : ReadAdvance<ReadIEReg, 0>;
117 def : ReadAdvance<ReadIM, 0>;
118 def : ReadAdvance<ReadIMA, 2, [WriteIM32, WriteIM64]>;
119 def : ReadAdvance<ReadID, 0>;
120 def : ReadAdvance<ReadExtrHi, 0>;
121 def : ReadAdvance<ReadST, 0>;
122 def : ReadAdvance<ReadAdrBase, 0>;
123 def : ReadAdvance<ReadVL
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/freebsd/contrib/llvm-project/llvm/lib/MCA/HardwareUnits/
H A DRegisterFile.cpp524 int ReadAdvance = STI.getReadAdvanceCycles(SC, RD.UseIndex, WriteResID); in collectWrites() local
525 if (ReadAdvance < 0) { in collectWrites()
527 if (Elapsed < static_cast<unsigned>(-ReadAdvance)) in collectWrites()
539 int ReadAdvance = STI.getReadAdvanceCycles(SC, RD.UseIndex, WriteResID); in collectWrites() local
540 if (ReadAdvance < 0) { in collectWrites()
542 if (Elapsed < static_cast<unsigned>(-ReadAdvance)) in collectWrites()
582 int ReadAdvance = STI.getReadAdvanceCycles(SC, RD.UseIndex, WriteResID); in checkRAWHazards() local
593 int CyclesLeft = WS->getCyclesLeft() - ReadAdvance; in checkRAWHazards()
643 int ReadAdvance = STI.getReadAdvanceCycles(SC, RD.UseIndex, WriteResID); in addRegisterRead() local
644 WS.addUser(WR.getSourceIndex(), &RS, ReadAdvance); in addRegisterRead()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleM4.td100 def : ReadAdvance<ReadALU, 0>;
101 def : ReadAdvance<ReadALUsr, 0>;
102 def : ReadAdvance<ReadMUL, 0>;
103 def : ReadAdvance<ReadMAC, 0>;
134 def : ReadAdvance<ReadFPMUL, 0>;
135 def : ReadAdvance<ReadFPMAC, 0>;
H A DARMScheduleM7.td36 // ReadAdvance<0> (the default) for their source operands and Latency = 1.
175 def : ReadAdvance<ReadALUsr, 0>;
176 def : ReadAdvance<ReadMUL, 0>;
177 def : ReadAdvance<ReadMAC, 1>;
178 def : ReadAdvance<ReadALU, 0>;
179 def : ReadAdvance<ReadFPMUL, 0>;
180 def : ReadAdvance<ReadFPMAC, 3>;
H A DARMScheduleR52.td87 def : ReadAdvance<ReadALU, 1>; // Operand needed in EX1 stage
88 def : ReadAdvance<ReadALUsr, 0>; // Shift operands needed in ISS
89 def : ReadAdvance<ReadMUL, 0>;
90 def : ReadAdvance<ReadMAC, 0>;
127 def : ReadAdvance<ReadFPMUL, 1>; // mul operand read in F1
128 def : ReadAdvance<ReadFPMAC, 1>; // fp-mac operand read in F1
134 def : ReadAdvance<R52Read_ISS, 0>;
135 def : ReadAdvance<R52Read_EX1, 1>;
136 def : ReadAdvance<R52Read_EX2, 2>;
137 def : ReadAdvance<R52Read_F
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/freebsd/contrib/llvm-project/llvm/lib/MCA/
H A DInstruction.cpp72 void WriteState::addUser(unsigned IID, ReadState *User, int ReadAdvance) { in addUser() argument
77 unsigned ReadCycles = std::max(0, CyclesLeft - ReadAdvance); in addUser()
82 Users.emplace_back(User, ReadAdvance); in addUser()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ScheduleSLM.td50 def : ReadAdvance<ReadAfterLd, 3>;
51 def : ReadAdvance<ReadAfterVecLd, 3>;
52 def : ReadAdvance<ReadAfterVecXLd, 3>;
53 def : ReadAdvance<ReadAfterVecYLd, 3>;
55 def : ReadAdvance<ReadInt2Fpu, 0>;

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