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Searched refs:Ra (Results 1 – 18 of 18) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64PBQPRegAlloc.cpp154 unsigned Ra) { in addIntraChainConstraint() argument
155 if (Rd == Ra) in addIntraChainConstraint()
160 if (Register::isPhysicalRegister(Rd) || Register::isPhysicalRegister(Ra)) { in addIntraChainConstraint()
164 << Register::isPhysicalRegister(Ra) << '\n'); in addIntraChainConstraint()
169 PBQPRAGraph::NodeId node2 = G.getMetadata().getNodeIdForVReg(Ra); in addIntraChainConstraint()
182 const LiveInterval &la = LIs.getInterval(Ra); in addIntraChainConstraint()
238 unsigned Ra) { in addInterChainConstraint() argument
242 if (Chains.count(Ra)) { in addInterChainConstraint()
243 if (Rd != Ra) { in addInterChainConstraint()
244 LLVM_DEBUG(dbgs() << "Moving acc chain from " << printReg(Ra, TRI) in addInterChainConstraint()
[all …]
H A DAArch64PBQPRegAlloc.h32 bool addIntraChainConstraint(PBQPRAGraph &G, unsigned Rd, unsigned Ra);
35 void addInterChainConstraint(PBQPRAGraph &G, unsigned Rd, unsigned Ra);
H A DAArch64InstrInfo.td2460 def : Pat<(i64 (add (mul (sext GPR32:$Rn), (s64imm_32bit:$C)), GPR64:$Ra)),
2461 (SMADDLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>;
2462 def : Pat<(i64 (add (mul (zext GPR32:$Rn), (i64imm_32bit:$C)), GPR64:$Ra)),
2463 (UMADDLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>;
2465 GPR64:$Ra)),
2467 (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>;
2469 def : Pat<(i64 (sub GPR64:$Ra, (mul (sext GPR32:$Rn), (s64imm_32bit:$C)))),
2470 (SMSUBLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>;
2471 def : Pat<(i64 (sub GPR64:$Ra, (mul (zext GPR32:$Rn), (i64imm_32bit:$C)))),
2472 (UMSUBLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), GPR64:$Ra)>;
[all …]
H A DAArch64InstrFormats.td2602 : I<(outs addtype:$Rd), (ins multype:$Rn, multype:$Rm, addtype:$Ra),
2603 asm, "\t$Rd, $Rn, $Rm, $Ra", "", pattern> {
2607 bits<5> Ra;
2612 let Inst{14-10} = Ra;
2633 [(set GPR64:$Rd, (AccNode GPR64:$Ra,
2654 // The Ra field of SMULH and UMULH is unused: it should be assembled as 31
5484 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, regtype: $Ra),
5485 asm, "\t$Rd, $Rn, $Rm, $Ra", "", pat>,
5490 bits<5> Ra;
5495 let Inst{14-10} = Ra;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMCCodeEmitter.cpp125 MCRegister Ra; in expandFunctionCall() local
128 Ra = RISCV::X6; in expandFunctionCall()
132 Ra = RISCV::X7; in expandFunctionCall()
135 Ra = MI.getOperand(0).getReg(); in expandFunctionCall()
138 Ra = RISCV::X1; in expandFunctionCall()
141 Ra = MI.getOperand(0).getReg(); in expandFunctionCall()
150 TmpInst = MCInstBuilder(RISCV::AUIPC).addReg(Ra).addExpr(CallExpr); in expandFunctionCall()
157 TmpInst = MCInstBuilder(RISCV::JALR).addReg(RISCV::X0).addReg(Ra).addImm(0); in expandFunctionCall()
160 TmpInst = MCInstBuilder(RISCV::JALR).addReg(Ra).addReg(Ra).addImm(0); in expandFunctionCall()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCExpandPseudos.cpp90 Register Ra = MF.getRegInfo().createVirtualRegister(&ARC::GPR32RegClass); in expandCTLZ() local
93 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), TII->get(ARC::FLS_f_rr), Ra) in expandCTLZ()
98 .addReg(Ra); in expandCTLZ()
/freebsd/crypto/openssl/crypto/ec/asm/
H A Decp_nistz256-x86_64.pl2558 my ($ONE,$INDEX,$Ra,$Rb,$Rc,$Rd,$Re,$Rf)=map("%xmm$_",(0..7));
2621 pxor $Ra, $Ra
2648 por $T0a, $Ra
2662 movdqu $Ra, 16*0($val)
2741 pxor $Ra, $Ra
2762 por $T0a, $Ra
2773 movdqu $Ra, 16*0($val)
2800 my ($TWO,$INDEX,$Ra,$Rb,$Rc)=map("%ymm$_",(0..4));
2833 vpxor $Ra, $Ra, $Ra
2841 vpermd $INDEX, $Ra, $INDEX
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrInfo.td4064 def USADA8 : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
4066 "\t$Rd, $Rn, $Rm, $Ra",
4067 [(set GPR:$Rd, (int_arm_usada8 GPR:$Rn, GPR:$Rm, GPR:$Ra))]>,
4072 bits<4> Ra;
4076 let Inst{15-12} = Ra;
4348 (ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra),
4349 IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
4350 [(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))]>,
4353 bits<4> Ra;
4354 let Inst{15-12} = Ra;
[all …]
H A DARMInstrThumb2.td677 bits<4> Ra;
680 let Inst{15-12} = Ra;
2684 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary,
2685 "usada8", "\t$Rd, $Rn, $Rm, $Ra",
2686 [(set rGPR:$Rd, (int_arm_usada8 rGPR:$Rn, rGPR:$Rm, rGPR:$Ra))]>,
3044 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
3049 : T2FourReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
3050 opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>,
3061 rGPR:$Ra))]>;
3063 [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn,
[all …]
H A DARMInstrFormats.td987 // MSW multiple w/ Ra operand
991 bits<4> Ra;
992 let Inst{15-12} = Ra;
1017 // AMulxyI with Ra operand
1021 bits<4> Ra;
1022 let Inst{15-12} = Ra;
/freebsd/tools/regression/iscsi/
H A Discsi-test.sh152 check iscsictl -Ra
764 check iscsictl -Ra
/freebsd/contrib/tzdata/
H A Dsouthamerica1675 # From Carlos Raúl Perasso via Jesper Nørgaard Welen (2006-10-13)
1679 # From Carlos Raúl Perasso (2010-02-18):
1697 # From Carlos Raúl Perasso (2013-03-15):
1700 # From Carlos Raúl Perasso (2014-02-28):
1707 # From Carlos Raúl Perasso (2023-07-27):
H A DNEWS3269 (Thanks to Carlos Raúl Perasso.)
3994 Paraguay's 2014 DST will be as predicted. (Thanks to Carlos Raúl Perasso.)
4479 (Thanks to Carlos Raúl Perasso.)
H A Dnorthamerica2602 # From Carlos Raúl Perasso (2015-02-02):
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonPatterns.td955 def: Pat<(select (i1 (setult F32:$Ra, F32:$Rb)), F32:$Rs, F32:$Rt),
956 (C2_mux (F2_sfcmpgt F32:$Rb, F32:$Ra), F32:$Rs, F32:$Rt)>;
957 def: Pat<(select (i1 (setult F64:$Ra, F64:$Rb)), F64:$Rs, F64:$Rt),
958 (C2_vmux (F2_dfcmpgt F64:$Rb, F64:$Ra), F64:$Rs, F64:$Rt)>;
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp2744 unsigned Ra = fieldFromInstruction(Insn, 12, 4); in DecodeSMLAInstruction() local
2756 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) in DecodeSMLAInstruction()
/freebsd/contrib/tzcode/
H A DNEWS
/freebsd/contrib/sendmail/
H A DPGPKEYS111 V9xOCqCWvcJ8gC+Ra+h5PN+ESy4Qqo771fNThV4C5QMQ6t8I+JPiepI+H4U19zxb