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Searched refs:RSB (Results 1 – 15 of 15) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Dac100.txt9 - reg: The I2C slave address or RSB hardware address for the chip
H A Daxp20x.txt32 - reg: The I2C slave address or RSB hardware address for the AXP chip
/freebsd/sys/contrib/device-tree/src/arm64/allwinner/
H A Dsun50i-a64-olinuxino.dts177 * and the RSB Bus.
206 /* VCC-PL is powered by aldo2 but we cannot add it as the RSB */
H A Dsun50i-a100-allwinner-perf1.dts37 * and the RSB Bus.
H A Dsun50i-h6-beelink-gs1.dts163 * and the RSB Bus.
H A Dsun50i-h64-remix-mini-pc.dts181 * dependency between pinctrl, the regulator and the RSB Bus.
H A Dsun50i-a64-pinebook.dts236 * and the RSB Bus.
H A Dsun50i-a64-pinephone.dtsi301 * and the RSB Bus.
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp95 unsigned RSB; member
309 STORE_OPCODE(RSB, RSBri); in OpcodeCache()
897 BuildMI(MBB, InsertBefore, I.getDebugLoc(), TII.get(Opcodes.RSB)) in select()
H A DARMScheduleM7.td326 (instregex "t2(ADC|ADDS|ADD|BIC|EOR|ORN|ORR|RSBS|RSB|SBC|SUBS)rs$",
H A DARMScheduleSwift.td129 // ADC,ADD,NEG,RSB,RSC,SBC,SUB,ADR
H A DARMScheduleA57.td171 // RSB{S}, RSC{S}, SUB{S}, SBC{S}, TEQ, TST
H A DARMScheduleA9.td2299 def :ItinRW<[WriteALUsi, ReadDefault, A9ReadALU], [IIC_iALUsir]>; // RSB
H A DARMInstrThumb2.td2477 // RSB
5202 // Alias for RSB with and without the ".w" optional width specifier, with and
H A DARMInstrInfo.td3885 defm RSB : AsI1_rbin_irs<0b0011, "rsb",