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Searched refs:RISCVTargetLowering (Results 1 – 10 of 10) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVCallLowering.h24 class RISCVTargetLowering; variable
29 RISCVCallLowering(const RISCVTargetLowering &TLI);
H A DRISCVCallLowering.cpp32 RISCVTargetLowering::RISCVCCAssignFn *RISCVAssignFn;
41 RISCVTargetLowering::RISCVCCAssignFn *RISCVAssignFn_, bool IsRet, in RISCVOutgoingValueAssigner()
178 RISCVTargetLowering::RISCVCCAssignFn *RISCVAssignFn;
187 RISCVTargetLowering::RISCVCCAssignFn *RISCVAssignFn_, bool IsRet, in RISCVIncomingValueAssigner()
316 RISCVCallLowering::RISCVCallLowering(const RISCVTargetLowering &TLI) in RISCVCallLowering()
414 RVVArgDispatcher Dispatcher{&MF, getTLI<RISCVTargetLowering>(), in lowerReturnVal()
544 RVVArgDispatcher Dispatcher{&MF, getTLI<RISCVTargetLowering>(), in lowerFormalArguments()
610 RVVArgDispatcher ArgDispatcher{&MF, getTLI<RISCVTargetLowering>(), in lowerCall()
642 RVVArgDispatcher RetDispatcher{&MF, getTLI<RISCVTargetLowering>(), in lowerCall()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp83 RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, in RISCVTargetLowering() function in RISCVTargetLowering
1518 EVT RISCVTargetLowering::getSetCCResultType(const DataLayout &DL, in getSetCCResultType()
1529 MVT RISCVTargetLowering::getVPExplicitVectorLengthTy() const { in getVPExplicitVectorLengthTy()
1534 bool RISCVTargetLowering::shouldExpandGetVectorLength(EVT TripCountVT, in shouldExpandGetVectorLength()
1560 bool RISCVTargetLowering::shouldExpandCttzElements(EVT VT) const { in shouldExpandCttzElements()
1565 bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, in getTgtMemIntrinsic()
1605 Info.flags |= RISCVTargetLowering::getTargetMMOFlags(I); in getTgtMemIntrinsic()
1837 bool RISCVTargetLowering::isLegalAddressingMode(const DataLayout &DL, in isLegalAddressingMode()
1867 bool RISCVTargetLowering in isLegalICmpImmediate()
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H A DRISCVISelDAGToDAG.cpp345 RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); in selectVLSEG()
370 unsigned SubRegIdx = RISCVTargetLowering::getSubregIndexByMVT(VT, I); in selectVLSEG()
385 RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); in selectVLSEGFF()
411 unsigned SubRegIdx = RISCVTargetLowering::getSubregIndexByMVT(VT, I); in selectVLSEGFF()
427 RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); in selectVLXSEG()
446 RISCVII::VLMUL IndexLMUL = RISCVTargetLowering::getLMUL(IndexVT); in selectVLXSEG()
463 unsigned SubRegIdx = RISCVTargetLowering::getSubregIndexByMVT(VT, I); in selectVLXSEG()
482 RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); in selectVSSEG()
512 RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT); in selectVSXSEG()
528 RISCVII::VLMUL IndexLMUL = RISCVTargetLowering::getLMUL(IndexVT); in selectVSXSEG()
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H A DRISCVSubtarget.h88 RISCVTargetLowering TLInfo;
116 const RISCVTargetLowering *getTargetLowering() const override { in getTargetLowering()
H A DRISCVISelLowering.h481 class RISCVTargetLowering : public TargetLowering {
485 explicit RISCVTargetLowering(const TargetMachine &TM,
902 const RISCVTargetLowering &TLI,
1073 RVVArgDispatcher(const MachineFunction *MF, const RISCVTargetLowering *TLI, in RVVArgDispatcher()
1089 const RISCVTargetLowering *TLI = nullptr;
1104 bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI,
1110 bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI,
H A DRISCVTargetTransformInfo.h36 const RISCVTargetLowering *TLI;
39 const RISCVTargetLowering *getTLI() const { return TLI; } in getTLI()
H A DRISCVGatherScatterLowering.cpp38 const RISCVTargetLowering *TLI = nullptr;
H A DRISCVInstrInfoA.td123 // RISCVTargetLowering::{emitLeadingFence,emitTrailingFence}.
H A DRISCVTargetTransformInfo.cpp1136 return RISCVTargetLowering::computeVLMAX(VectorBits, EltSize, MinSize); in getEstimatedVLFor()