Lines Matching refs:RISCVTargetLowering
83 RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
1518 EVT RISCVTargetLowering::getSetCCResultType(const DataLayout &DL,
1529 MVT RISCVTargetLowering::getVPExplicitVectorLengthTy() const {
1534 bool RISCVTargetLowering::shouldExpandGetVectorLength(EVT TripCountVT,
1560 bool RISCVTargetLowering::shouldExpandCttzElements(EVT VT) const {
1565 bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
1605 Info.flags |= RISCVTargetLowering::getTargetMMOFlags(I);
1837 bool RISCVTargetLowering::isLegalAddressingMode(const DataLayout &DL,
1867 bool RISCVTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
1871 bool RISCVTargetLowering::isLegalAddImmediate(int64_t Imm) const {
1880 bool RISCVTargetLowering::isTruncateFree(Type *SrcTy, Type *DstTy) const {
1888 bool RISCVTargetLowering::isTruncateFree(EVT SrcVT, EVT DstVT) const {
1899 bool RISCVTargetLowering::isTruncateFree(SDValue Val, EVT VT2) const {
1914 bool RISCVTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
1929 bool RISCVTargetLowering::isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const {
1933 bool RISCVTargetLowering::signExtendConstant(const ConstantInt *CI) const {
1937 bool RISCVTargetLowering::isCheapToSpeculateCttz(Type *Ty) const {
1941 bool RISCVTargetLowering::isCheapToSpeculateCtlz(Type *Ty) const {
1946 bool RISCVTargetLowering::isMaskAndCmp0FoldingBeneficial(
1962 bool RISCVTargetLowering::hasAndNotCompare(SDValue Y) const {
1973 bool RISCVTargetLowering::hasBitTest(SDValue X, SDValue Y) const {
1985 bool RISCVTargetLowering::shouldFoldSelectWithIdentityConstant(unsigned Opcode,
1997 bool RISCVTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
2027 bool RISCVTargetLowering::
2051 bool RISCVTargetLowering::canSplatOperand(unsigned Opcode, int Operand) const {
2081 bool RISCVTargetLowering::canSplatOperand(Instruction *I, int Operand) const {
2143 bool RISCVTargetLowering::shouldSinkOperands(
2190 bool RISCVTargetLowering::shouldScalarizeBinop(SDValue VecOp) const {
2212 bool RISCVTargetLowering::isOffsetFoldingLegal(
2228 std::pair<int, bool> RISCVTargetLowering::getLegalZfaFPImm(const APFloat &Imm,
2254 bool RISCVTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
2292 bool RISCVTargetLowering::isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
2339 MVT RISCVTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
2356 unsigned RISCVTargetLowering::getNumRegistersForCallingConv(LLVMContext &Context,
2368 unsigned RISCVTargetLowering::getVectorTypeBreakdownForCallingConv(
2449 RISCVII::VLMUL RISCVTargetLowering::getLMUL(MVT VT) {
2475 unsigned RISCVTargetLowering::getRegClassIDForLMUL(RISCVII::VLMUL LMul) {
2493 unsigned RISCVTargetLowering::getSubregIndexByMVT(MVT VT, unsigned Index) {
2516 unsigned RISCVTargetLowering::getRegClassIDForVecVT(MVT VT) {
2528 RISCVTargetLowering::decomposeSubvectorInsertExtractToSubRegs(
2560 bool RISCVTargetLowering::mergeStoresAfterLegalization(EVT VT) const {
2565 bool RISCVTargetLowering::isLegalElementTypeForRVV(EVT ScalarTy) const {
2589 unsigned RISCVTargetLowering::combineRepeatedFPDivisors() const {
2677 bool RISCVTargetLowering::useRVVForFixedLengthVectorVT(MVT VT) const {
2723 MVT RISCVTargetLowering::getContainerForFixedLengthVector(MVT VT) const {
2774 RISCVTargetLowering::computeVLMAXBounds(ContainerVT, Subtarget);
2813 SDValue RISCVTargetLowering::computeVLMax(MVT VecVT, const SDLoc &DL,
2821 RISCVTargetLowering::computeVLMAXBounds(MVT VecVT,
2830 RISCVTargetLowering::computeVLMAX(VectorBitsMax, EltSize, MinSize);
2834 RISCVTargetLowering::computeVLMAX(VectorBitsMin, EltSize, MinSize);
2847 bool RISCVTargetLowering::shouldExpandBuildVectorWithShuffles(
2852 InstructionCost RISCVTargetLowering::getLMULCost(MVT VT) const {
2863 RISCVVType::decodeVLMUL(RISCVTargetLowering::getLMUL(VT));
2878 InstructionCost RISCVTargetLowering::getVRGatherVVCost(MVT VT) const {
2885 InstructionCost RISCVTargetLowering::getVRGatherVICost(MVT VT) const {
2893 InstructionCost RISCVTargetLowering::getVSlideVXCost(MVT VT) const {
2901 InstructionCost RISCVTargetLowering::getVSlideVICost(MVT VT) const {
4159 switch (RISCVTargetLowering::getLMUL(ContainerVT)) {
5380 bool RISCVTargetLowering::isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const {
5403 RISCVTargetLowering::lowerCTLZ_CTTZ_ZERO_UNDEF(SDValue Op,
5428 // Legal types should have been checked in the RISCVTargetLowering
5519 SDValue RISCVTargetLowering::lowerVPCttzElements(SDValue Op,
5561 SDValue RISCVTargetLowering::expandUnalignedRVVLoad(SDValue Op,
5590 SDValue RISCVTargetLowering::expandUnalignedRVVStore(SDValue Op,
5758 SDValue RISCVTargetLowering::LowerIS_FPCLASS(SDValue Op,
6243 SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
7271 SDValue RISCVTargetLowering::emitFlushICache(SelectionDAG &DAG, SDValue InChain,
7306 SDValue RISCVTargetLowering::getAddr(NodeTy *N, SelectionDAG &DAG,
7376 SDValue RISCVTargetLowering::lowerGlobalAddress(SDValue Op,
7384 SDValue RISCVTargetLowering::lowerBlockAddress(SDValue Op,
7391 SDValue RISCVTargetLowering::lowerConstantPool(SDValue Op,
7398 SDValue RISCVTargetLowering::lowerJumpTable(SDValue Op,
7405 SDValue RISCVTargetLowering::getStaticTLSAddr(GlobalAddressSDNode *N,
7452 SDValue RISCVTargetLowering::getDynamicTLSAddr(GlobalAddressSDNode *N,
7484 SDValue RISCVTargetLowering::getTLSDescAddr(GlobalAddressSDNode *N,
7501 SDValue RISCVTargetLowering::lowerGlobalTLSAddress(SDValue Op,
7693 SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
7871 SDValue RISCVTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
7894 SDValue RISCVTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const {
7909 SDValue RISCVTargetLowering::lowerFRAMEADDR(SDValue Op,
7932 SDValue RISCVTargetLowering::lowerRETURNADDR(SDValue Op,
7962 SDValue RISCVTargetLowering::lowerShiftLeftParts(SDValue Op,
8001 SDValue RISCVTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
8055 SDValue RISCVTargetLowering::lowerVectorMaskSplat(SDValue Op,
8081 SDValue RISCVTargetLowering::lowerSPLAT_VECTOR_PARTS(SDValue Op,
8111 SDValue RISCVTargetLowering::lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG,
8149 SDValue RISCVTargetLowering::lowerFixedLengthVectorExtendToRVV(
8179 SDValue RISCVTargetLowering::lowerVectorMaskTruncLike(SDValue Op,
8231 SDValue RISCVTargetLowering::lowerVectorTruncLike(SDValue Op,
8294 RISCVTargetLowering::lowerStrictFPExtendOrRoundLike(SDValue Op,
8343 RISCVTargetLowering::lowerVectorFPExtendOrRoundLike(SDValue Op,
8446 SDValue RISCVTargetLowering::lowerINSERT_VECTOR_ELT(SDValue Op,
8614 SDValue RISCVTargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op,
8853 RISCVTargetLowering::computeVLMAXBounds(VT, Subtarget);
8860 RISCVII::VLMUL Lmul = RISCVTargetLowering::getLMUL(I32VT);
8875 RISCVII::VLMUL Lmul = RISCVTargetLowering::getLMUL(VT);
9079 SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
9403 SDValue RISCVTargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
9557 SDValue RISCVTargetLowering::LowerINTRINSIC_VOID(SDValue Op,
9711 SDValue RISCVTargetLowering::lowerVectorMaskVecReduction(SDValue Op,
9832 SDValue RISCVTargetLowering::lowerVECREDUCE(SDValue Op,
9918 SDValue RISCVTargetLowering::lowerFPVECREDUCE(SDValue Op,
9961 SDValue RISCVTargetLowering::lowerVPREDUCE(SDValue Op,
10011 SDValue RISCVTargetLowering::lowerINSERT_SUBVECTOR(SDValue Op,
10135 RISCVTargetLowering::decomposeSubvectorInsertExtractToSubRegs(
10142 RISCVTargetLowering::decomposeSubvectorInsertExtractToSubRegs(
10248 SDValue RISCVTargetLowering::lowerEXTRACT_SUBVECTOR(SDValue Op,
10358 RISCVTargetLowering::decomposeSubvectorInsertExtractToSubRegs(
10365 RISCVTargetLowering::decomposeSubvectorInsertExtractToSubRegs(
10450 SDValue RISCVTargetLowering::lowerVECTOR_DEINTERLEAVE(SDValue Op,
10526 SDValue RISCVTargetLowering::lowerVECTOR_INTERLEAVE(SDValue Op,
10617 SDValue RISCVTargetLowering::lowerSTEP_VECTOR(SDValue Op,
10647 SDValue RISCVTargetLowering::lowerVECTOR_REVERSE(SDValue Op,
10661 RISCVTargetLowering::computeVLMAX(VectorBitsMax, EltSize, MinSize);
10721 SDValue RISCVTargetLowering::lowerVECTOR_SPLICE(SDValue Op,
10756 RISCVTargetLowering::lowerFixedLengthVectorLoadToRVV(SDValue Op,
10773 RISCVTargetLowering::computeVLMAXBounds(ContainerVT, Subtarget);
10805 RISCVTargetLowering::lowerFixedLengthVectorStoreToRVV(SDValue Op,
10836 RISCVTargetLowering::computeVLMAXBounds(ContainerVT, Subtarget);
10857 SDValue RISCVTargetLowering::lowerMaskedLoad(SDValue Op,
10922 SDValue RISCVTargetLowering::lowerMaskedStore(SDValue Op,
10988 RISCVTargetLowering::lowerFixedLengthVectorSetccToRVV(SDValue Op,
11012 SDValue RISCVTargetLowering::lowerVectorStrictFSetcc(SDValue Op,
11101 SDValue RISCVTargetLowering::lowerABS(SDValue Op, SelectionDAG &DAG) const {
11138 SDValue RISCVTargetLowering::lowerFixedLengthVectorFCOPYSIGNToRVV(
11159 SDValue RISCVTargetLowering::lowerFixedLengthVectorSelectToRVV(
11183 SDValue RISCVTargetLowering::lowerToScalableOp(SDValue Op,
11237 SDValue RISCVTargetLowering::lowerVPOp(SDValue Op, SelectionDAG &DAG) const {
11292 SDValue RISCVTargetLowering::lowerVPExtMaskOp(SDValue Op,
11325 SDValue RISCVTargetLowering::lowerVPSetCCMaskOp(SDValue Op,
11405 SDValue RISCVTargetLowering::lowerVPFPIntConvOp(SDValue Op,
11539 RISCVTargetLowering::lowerVPSpliceExperimental(SDValue Op,
11622 SDValue RISCVTargetLowering::lowerVPSplatExperimental(SDValue Op,
11646 RISCVTargetLowering::lowerVPReverseExperimental(SDValue Op,
11686 RISCVTargetLowering::computeVLMAX(VectorBitsMax, EltSize, MinSize);
11766 SDValue RISCVTargetLowering::lowerLogicVPOp(SDValue Op,
11792 SDValue RISCVTargetLowering::lowerVPStridedLoad(SDValue Op,
11838 SDValue RISCVTargetLowering::lowerVPStridedStore(SDValue Op,
11881 SDValue RISCVTargetLowering::lowerMaskedGather(SDValue Op,
11980 SDValue RISCVTargetLowering::lowerMaskedScatter(SDValue Op,
12060 SDValue RISCVTargetLowering::lowerGET_ROUNDING(SDValue Op,
12091 SDValue RISCVTargetLowering::lowerSET_ROUNDING(SDValue Op,
12123 SDValue RISCVTargetLowering::lowerEH_DWARF_CFA(SDValue Op,
12187 void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
16033 const RISCVTargetLowering &TLI) {
16091 const RISCVTargetLowering &TLI) {
16163 const RISCVTargetLowering &TLI) {
16360 RISCVTargetLowering::DAGCombinerInfo &DCI) {
16657 SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
17634 bool RISCVTargetLowering::shouldTransformSignedTruncationCheck(
17653 bool RISCVTargetLowering::isDesirableToCommuteWithShift(
17705 bool RISCVTargetLowering::targetShrinkDemandedConstant(
17810 void RISCVTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
17951 unsigned RISCVTargetLowering::ComputeNumSignBitsForTargetNode(
18037 bool RISCVTargetLowering::canCreateUndefOrPoisonForTargetNode(
18055 RISCVTargetLowering::getTargetConstantFromLoad(LoadSDNode *Ld) const {
18750 RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
18845 void RISCVTargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
18997 bool IsRet, Type *OrigTy, const RISCVTargetLowering &TLI,
19246 void RISCVTargetLowering::analyzeInputArgs(
19284 void RISCVTargetLowering::analyzeOutputArgs(
19350 const RISCVTargetLowering &TLI) {
19486 const RISCVTargetLowering &TLI,
19660 SDValue RISCVTargetLowering::LowerFormalArguments(
19827 bool RISCVTargetLowering::isEligibleForTailCallOptimization(
19893 SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
20194 bool RISCVTargetLowering::CanLowerReturn(
20215 RISCVTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
20316 void RISCVTargetLowering::validateCCReservedRegs(
20331 bool RISCVTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
20368 bool RISCVTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
20372 const char *RISCVTargetLowering::getTargetNodeName(unsigned Opcode) const {
20638 RISCVTargetLowering::ConstraintType
20639 RISCVTargetLowering::getConstraintType(StringRef Constraint) const {
20664 RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
20869 RISCVTargetLowering::getInlineAsmMemConstraint(StringRef ConstraintCode) const {
20883 void RISCVTargetLowering::LowerAsmOperandForConstraint(
20923 Instruction *RISCVTargetLowering::emitLeadingFence(IRBuilderBase &Builder,
20939 Instruction *RISCVTargetLowering::emitTrailingFence(IRBuilderBase &Builder,
20957 RISCVTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
21036 Value *RISCVTargetLowering::emitMaskedAtomicRMWIntrinsic(
21096 RISCVTargetLowering::shouldExpandAtomicCmpXchgInIR(
21109 Value *RISCVTargetLowering::emitMaskedAtomicCmpXchgIntrinsic(
21131 bool RISCVTargetLowering::shouldRemoveExtendFromGSIndex(SDValue Extend,
21141 bool RISCVTargetLowering::shouldConvertFpToSat(unsigned Op, EVT FPVT,
21158 unsigned RISCVTargetLowering::getJumpTableEncoding() const {
21168 const MCExpr *RISCVTargetLowering::LowerCustomJumpTableEntry(
21176 bool RISCVTargetLowering::isVScaleKnownToBeAPowerOfTwo() const {
21188 bool RISCVTargetLowering::getIndexedAddressParts(SDNode *Op, SDValue &Base,
21224 bool RISCVTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
21246 bool RISCVTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
21293 bool RISCVTargetLowering::isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
21315 ISD::NodeType RISCVTargetLowering::getExtendForAtomicCmpSwapArg() const {
21320 Register RISCVTargetLowering::getExceptionPointerRegister(
21325 Register RISCVTargetLowering::getExceptionSelectorRegister(
21330 bool RISCVTargetLowering::shouldExtendTypeInLibCall(EVT Type) const {
21340 bool RISCVTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
21347 bool RISCVTargetLowering::decomposeMulByConstant(LLVMContext &Context, EVT VT,
21386 bool RISCVTargetLowering::isMulAddWithConstProfitable(SDValue AddNode,
21409 bool RISCVTargetLowering::allowsMisalignedMemoryAccesses(
21436 EVT RISCVTargetLowering::getOptimalMemOpType(const MemOp &Op,
21478 bool RISCVTargetLowering::splitValueIntoRegisterParts(
21533 SDValue RISCVTargetLowering::joinRegisterPartsIntoValue(
21579 bool RISCVTargetLowering::isIntDivCheap(EVT VT, AttributeList Attr) const {
21587 bool RISCVTargetLowering::preferScalarizeSplat(SDNode *N) const {
21604 Value *RISCVTargetLowering::getIRStackGuard(IRBuilderBase &IRB) const {
21619 bool RISCVTargetLowering::isLegalInterleavedAccessType(
21657 bool RISCVTargetLowering::isLegalStridedLoadStore(EVT DataType,
21695 bool RISCVTargetLowering::lowerInterleavedLoad(
21747 bool RISCVTargetLowering::lowerInterleavedStore(StoreInst *SI,
21786 bool RISCVTargetLowering::lowerDeinterleaveIntrinsicToLoad(IntrinsicInst *DI,
21836 bool RISCVTargetLowering::lowerInterleaveIntrinsicToStore(IntrinsicInst *II,
21883 RISCVTargetLowering::EmitKCFICheck(MachineBasicBlock &MBB,
21904 RISCVTargetLowering::getRegisterByName(const char *RegName, LLT VT,
21920 RISCVTargetLowering::getTargetMMOFlags(const Instruction &I) const {
21955 RISCVTargetLowering::getTargetMMOFlags(const MemSDNode &Node) const {
21964 bool RISCVTargetLowering::areTwoSDNodeTargetMMOFlagsMergeable(
21969 bool RISCVTargetLowering::isCtpopFast(EVT VT) const {
21978 unsigned RISCVTargetLowering::getCustomCtpopCost(EVT VT,
21983 bool RISCVTargetLowering::fallBackToDAGISel(const Instruction &Inst) const {
22011 RISCVTargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
22031 bool RISCVTargetLowering::shouldFoldSelectWithSingleBitTest(
22038 unsigned RISCVTargetLowering::getMinimumJumpTableEntries() const {
22217 SDValue RISCVTargetLowering::expandIndirectJTBranch(const SDLoc &dl,