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Searched refs:RISCVAsmBackend (Results 1 – 5 of 5) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVAsmBackend.cpp39 std::optional<MCFixupKind> RISCVAsmBackend::getFixupKind(StringRef Name) const { in getFixupKind()
57 RISCVAsmBackend::getFixupKindInfo(MCFixupKind Kind) const { in getFixupKindInfo()
114 bool RISCVAsmBackend::shouldForceRelocation(const MCAssembler &Asm, in shouldForceRelocation()
141 bool RISCVAsmBackend::fixupNeedsRelaxationAdvanced( in fixupNeedsRelaxationAdvanced()
175 void RISCVAsmBackend::relaxInstruction(MCInst &Inst, in relaxInstruction()
204 bool RISCVAsmBackend::relaxDwarfLineAddr(const MCAssembler &Asm, in relaxDwarfLineAddr()
270 bool RISCVAsmBackend::relaxDwarfCFA(const MCAssembler &Asm, in relaxDwarfCFA()
332 std::pair<bool, bool> RISCVAsmBackend::relaxLEB128(const MCAssembler &Asm, in relaxLEB128()
347 unsigned RISCVAsmBackend::getRelaxedOpcode(unsigned Op) const { in getRelaxedOpcode()
373 bool RISCVAsmBackend::mayNeedRelaxation(const MCInst &Inst, in mayNeedRelaxation()
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H A DRISCVAsmBackend.h24 class RISCVAsmBackend : public MCAsmBackend {
32 RISCVAsmBackend(const MCSubtargetInfo &STI, uint8_t OSABI, bool Is64Bit, in RISCVAsmBackend() function
38 ~RISCVAsmBackend() override = default;
H A DRISCVELFStreamer.cpp37 auto &MAB = static_cast<RISCVAsmBackend &>(MCA.getBackend()); in RISCVTargetELFStreamer()
47 static_cast<RISCVAsmBackend &>(MAB).setForceRelocs(); in RISCVTargetELFStreamer()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp2705 RISCVAsmBackend &MAB = in ParseInstruction()
2706 static_cast<RISCVAsmBackend &>(Assembler->getBackend()); in ParseInstruction()
/freebsd/lib/clang/libllvm/
H A DMakefile1553 SRCS_MIN+= Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp