39 std::optional<MCFixupKind> RISCVAsmBackend::getFixupKind(StringRef Name) const {  in getFixupKind()
57 RISCVAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {  in getFixupKindInfo()
114 bool RISCVAsmBackend::shouldForceRelocation(const MCAssembler &Asm,  in shouldForceRelocation()
141 bool RISCVAsmBackend::fixupNeedsRelaxationAdvanced(  in fixupNeedsRelaxationAdvanced()
175 void RISCVAsmBackend::relaxInstruction(MCInst &Inst,  in relaxInstruction()
204 bool RISCVAsmBackend::relaxDwarfLineAddr(const MCAssembler &Asm,  in relaxDwarfLineAddr()
270 bool RISCVAsmBackend::relaxDwarfCFA(const MCAssembler &Asm,  in relaxDwarfCFA()
332 std::pair<bool, bool> RISCVAsmBackend::relaxLEB128(const MCAssembler &Asm,  in relaxLEB128()
347 unsigned RISCVAsmBackend::getRelaxedOpcode(unsigned Op) const {  in getRelaxedOpcode()
373 bool RISCVAsmBackend::mayNeedRelaxation(const MCInst &Inst,  in mayNeedRelaxation()
378 bool RISCVAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,  in writeNopData()
519 bool RISCVAsmBackend::evaluateTargetFixup(const MCAssembler &Asm,  in evaluateTargetFixup()
579 bool RISCVAsmBackend::handleAddSubRelocations(const MCAssembler &Asm,  in handleAddSubRelocations()
625 void RISCVAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,  in applyFixup()
659 bool RISCVAsmBackend::shouldInsertExtraNopBytesForCodeAlign(  in shouldInsertExtraNopBytesForCodeAlign()
683 bool RISCVAsmBackend::shouldInsertFixupForCodeAlign(MCAssembler &Asm,  in shouldInsertFixupForCodeAlign()
711 RISCVAsmBackend::createObjectTargetWriter() const {  in createObjectTargetWriter()
721   return new RISCVAsmBackend(STI, OSABI, TT.isArch64Bit(), Options);  in createRISCVAsmBackend()